An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization. - Sungmin Bae; Yong Cheol Peter Cho; Sungho Park; Kevin M. Irick; Yongseok Jin; Vijaykrishnan Narayanan (FCCM, 2011)

Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA. - Yong Cheol Peter Cho; Sungmin Bae; Yongseok Jin; Kevin M. Irick; Vijaykrishnan Narayanan (FPL, 2011)

A reconfigurable platform for the design and verification of domain-specific accelerators. - Sungho Park; Yong Cheol Peter Cho; Kevin M. Irick; Vijaykrishnan Narayanan (ASP-DAC, 2012)

Multiresolution Gabor Feature Extraction for Real Time Applications. - Yong Cheol Peter Cho; Nandhini Chandramoorthy; Kevin M. Irick; Vijaykrishnan Narayanan (SiPS, 2012)

Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems. - Siddharth Advani; Nandhini Chandramoorthy; Karthik Swaminathan; Kevin M. Irick; Yong Cheol Peter Cho; Jack Sampson; Vijaykrishnan Narayanan (ICCD, 2014)

Accelerating Multiresolution Gabor Feature Extraction for Real Time Vision Applications. - Yong Cheol Peter Cho; Nandhini Chandramoorthy; Kevin M. Irick; Vijaykrishnan Narayanan (J. Signal Process. Syst., 2014)

A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics. - Jinho Han; Youngsu Kwon; Yong Cheol Peter Cho; Hoi-Jun Yoo (A-SSCC, 2017)

A deep learning convolution architecture for simple embedded applications. - Chan Kim; Yong Cheol Peter Cho; Youngsu Kwon (ICCE-Berlin, 2017)

Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture. - Youngsu Kwon; Jeongmin Yang; Yong Cheol Peter Cho; Kyoung-Seon Shin; Jaehoon Chung; Jinho Han; Chun-Gi Lyuh; Hyun-Mi Kim; Chan Kim; Min-Seok Choi (AICAS, 2019)

Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator. - Chan Kim; In San Jeon; Young-Su Kwon; Hyun-Mi Kim; Chun-Gi Lyuh; Yong Cheol Peter Cho; Jeongmin Yang; Jaehoon Chung; Kyoung-Seon Shin; Jinho Han; Min-Seok Choi (ICCE-Berlin, 2019)

AI 32TFLOPS Autonomous Driving Processor on AI-Ware with Adaptive Power Saving. - Youngsu Kwon; Yong Cheol Peter Cho; Jeongmin Yang; Jaehoon Chung; Kyoung-Seon Shin; Jinho Han; Chan Kim; Chun-Gi Lyuh; Hyun-Mi Kim; In San Jeon; Min-Seok Choi (ISOCC, 2019)

HPC LINPACK Parameter Optimization on Homo-/Heterogeneous System of ARM Neoverse N1SDP. - Je-Seok Ham; Yong Cheol Peter Cho; Ju-Yeob Kim; Chun-Gi Lyuh; Jin-Kyu Kim; Jinho Han; Youngsu Kwon (HPC Asia, 2021)

Live Demonstration: A Neural Processor for AI Acceleration. - Hyeji Kim; Jaehoon Chung; Kyoung-Seon Shin; Chun-Gi Lyuh; Hyun-Mi Kim; Chan Kim; Yong Cheol Peter Cho; Jeongmin Yang; Je-Seok Ham; Minseok Choi; Jinho Han; Youngsu Kwon (ISCAS, 2021)

ArtBrain-K: AI Processor based-on 5-PetaFLOPS AI Server System. - Jinho Han; Chun-Gi Lyuh; Kyeongsun Shin; Hyun-Mi Kim; Hyunjeong Kwon; Jaehoon Chung; Yong Cheol Peter Cho; Jinkyu Kim; Jeonghui Suk; Chan Kim; Minseok Choi; Youngsu Kwon (AICAS, 2022)

M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations. - Won Jeon; Yong Cheol Peter Cho; Hyun-Mi Kim; Hyeji Kim; Jaehoon Chung; Ju-Yeob Kim; Miyoung Lee; Chun-Gi Lyuh; Jinho Han; Youngsu Kwon (AICAS, 2022)

Chiplet Heterogeneous-Integration AI Processor. - Youngsu Kwon; Jinho Han; Yong Cheol Peter Cho; Juyeob Kim; Jaehoon Chung; Jaewoong Choi; Sujin Park; Igyeong Kim; Hyunjeong Kwon; Jinkyu Kim; Hyunmi Kim; Won Jeon; et al. (ICEIC, 2023)