Single-ended D flip-flop with implicit scan mux for high performance mobile AP. - Min-Su Kim; Chunghee Kim; Yong-geol Kim; Ah-Reum Kim; Jikyum Kim; Juhyun Kang; Daeseong Lee; Changjun Choi; Ilsuk Suh; Jungyul Pyo; Youngmin Shin; Jae Cheol Son (SoCC, 2016)

Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling. - Min-Su Kim; Ah-Reum Kim; Yong-geol Kim; Chunghee Kim; Dong-Yeop Kim; Jong-Woo Kim; Daeseong Lee; Hyun Lee; Jungyul Pyo; Youngmin Shin; Jae Cheol Son (ISCAS, 2018)

An Area-Efficient True Single-Phase Clocked and Conditional Capture Flip-Flop for Ultra-Low-Power Operations in 7nm Fin-FET Process. - Hyun-chul Hwang; Min-su Kim; Daeseong Lee; Yong-geol Kim; Byung-Su Kim; Kun-hyuk Kang (VLSI Technology and Circuits, 2024)