A 4 Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement. - Tae-Ho Kim; Yong-Hwan Moon; Jin-Ku Kang (IEICE Trans. Electron., 2011)

A 2.2-mW 20-135-MHz False-Lock-Free DLL for Display Interface in 0.15-µm CMOS. - Yong-Hwan Moon; In-Seok Kong; Young-Soo Ryu; Jin-Ku Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Eye-open monitor using two-dimensional counter value profile. - Kyung-Sub Son; Yong-Hwan Moon; Sanghun Baek; Namyong Kim; Taek-Joon An; Jin-Ku Kang (IEICE Electron. Express, 2019)

A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort. - Yong-Hwan Moon; Jae-Wook Yoo; Young-Soo Ryu; Sang-Ho Kim; Kyung-Sub Son; Jin-Ku Kang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 0.42-3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition. - Kyung-Sub Son; Taek-Joon An; Yong-Hwan Moon; Jin-Ku Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2020)