A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8 V power supply. - Yong-In Park; Soundarapandian Karthikeyan; Frank (Ching-Yuh) Tsay; Eduardo Bartolome (ISCAS (1), 2001)

A 16-bit, 5MHz multi-bit sigma-delta ADC using adaptively randomized DWA. - Yong-In Park; S. Karthikeyan; Wem Ming Koe; Zhongnong Jiang; Tiak-Chean Tan (CICC, 2003)

Second order dynamic element matching technique for low oversampling delta sigma ADC. - A. K. Gupta; Edgar Sánchez-Sinencio; S. Karthikeyan; Wern Ming Koe; Yong-In Park (ISCAS, 2006)

Digital scheme for quantizer and integrator swing reduction in multibit sigma-delta modulator. - Wern Ming Koe; Franco Maloberti; James R. Hochschild; Soundarapandian Karthikeyan; Yong-In Park (ISCAS, 2006)

A 6.94-in. WVGA poly-Si TFT-LCD with integrated driver including sequential analog sampling circuits. - Kyoung Moon Lim; KyungEon Lee; Myoung Kee Baek; Bu Yeol Lee; Jin-Mo Yoon; Eugene Kim; Jae-Sung Yu; Yong-In Park; Yong Su Yoo; Young-Joo Kim; HoChul Kang; Chang-Dong Kim; et al. (Displays, 2006)

A high resolution Poly-Si TFT-LCD employing analog sample and hold driver. - Kyoung Moon Lim; KyungEon Lee; Myoung Kee Baek; Bu Yeol Lee; In-Hyuk Song; Jae-Sung Yu; Hye-Jin Lee; Kwang Ho Jang; Yong-In Park; Yong Su Yoo; HoChul Kang; Chang-Dong Kim; et al. (Displays, 2008)