AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing. - Vishal Sharma 004; Ju Eon Kim; Yong-Jun Jo; Yuzong Chen 001; Tony Tae-Hyoung Kim (ISCAS, 2021)

A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS. - Yong-Jun Jo; Ju Eon Kim; Kwang-Hyun Baek; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Based Digital Compute-in-Memory Macro for Accelerating CNNs. - Xin Zhang 025; Vishal Sharma 004; Yuncheng Lu; Yong-Jun Jo; Tony Tae-Hyoung Kim (A-SSCC, 2023)

DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC. - Yong-Jun Jo; Boon Peng Yap; Dong-Hyun Yoon; Hyunjoon Kim; Yuanjin Zheng; Tony Tae-Hyoung Kim (CICC, 2023)

Similarity-Aware Transposable SRAM Computation-In-Memory with Pulse-Based SAR ADC. - Yong-Jun Jo; Chufeng Yang; Yuanjin Zheng; Tony Tae-Hyoung Kim (A-SSCC, 2024)

A 65-nm 55.8-TOPS/W Compact 2T eDRAM-Based Compute-in-Memory Macro With Linear Calibration. - Xueyong Zhang; Yong-Jun Jo; Tony Tae-Hyoung Kim (IEEE Trans. Very Large Scale Integr. Syst., 2025)