Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells. - Yong-Jyun Hu; Yu-Jen Huang; Jin-Fu Li 001 (VTS, 2009)

Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells. - Jin-Fu Li 001; Yu-Jen Huang; Yong-Jyun Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. - Chi-Shin Chang; Hao-I Yang; Wei-Nan Liao; Yi-Wei Lin; Nan-Chun Lien; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Ming-Hsien Tu; Huan-Shun Huang; Yong-Jyun Hu; et al. (ISCAS, 2013)

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. - Wei-Nan Liao; Nan-Chun Lien; Chi-Shin Chang; Li-Wei Chu; Hao-I Yang; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang; Ming-Hsien Tu; Huan-Shun Huang; Jian-Hao Wang; Paul-Sen Kan; et al. (SoCC, 2013)

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. - Chao-Kuei Chung; Chien-Yu Lu; Zhi-Hao Chang; Shyh-Jye Jou; Ching-Te Chuang; Ming-Hsien Tu; Yu-Hsian Chen; Yong-Jyun Hu; Paul-Sen Kan; Huan-Shun Huang; Kuen-Di Lee; Yung-Shin Kao (SoCC, 2014)

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. - Nan-Chun Lien; Li-Wei Chu; Chien-Hen Chen; Hao-I Yang; Ming-Hsien Tu; Paul-Sen Kan; Yong-Jyun Hu; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)