Compiler-assisted data distribution for chip multiprocessors. - Yong Li 009; Ahmed Abousamra; Rami G. Melhem; Alex K. Jones (PACT, 2010)

Practically private: enabling high performance CMPs through compiler-assisted data classification. - Yong Li 009; Rami G. Melhem; Alex K. Jones (PACT, 2012)

Asymmetry of MTJ switching and its implication to STT-RAM designs. - Yaojun Zhang; Xiaobin Wang; Yong Li 009; Alex K. Jones; Yiran Chen 001 (DATE, 2012)

A software approach for combating asymmetries of non-volatile memories. - Yong Li 009; Yiran Chen 001; Alex K. Jones (ISLPED, 2012)

Cross-Layer Techniques for Optimizing Systems Utilizing Memories with Asymmetric Access Characteristics. - Yong Li 009; Alex K. Jones (ISVLSI, 2012)

Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration. - Yong Li 009; Yaojun Zhang; Yiran Chen 001; Alex K. Jones (IEEE Embed. Syst. Lett., 2012)

Compiler-Assisted Data Distribution and Network Configuration for Chip Multiprocessors. - Yong Li 009; Ahmed Abousamra; Rami G. Melhem; Alex K. Jones (IEEE Trans. Parallel Distributed Syst., 2012)

PS-TLB: Leveraging page classification information for fast, scalable and efficient translation for future CMPs. - Yong Li 009; Rami G. Melhem; Alex K. Jones (ACM Trans. Archit. Code Optim., 2013)

C1C: A configurable, compiler-guided STT-RAM L1 cache. - Yong Li 009; Yaojun Zhang; Hai Li 001; Yiran Chen 001; Alex K. Jones (ACM Trans. Archit. Code Optim., 2013)

STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. - Xiaoxiao Liu 001; Yong Li 009; Yaojun Zhang; Alex K. Jones; Yiran Chen 001 (ASP-DAC, 2014)

Prefetching techniques for STT-RAM based last-level cache in CMP systems. - Mengjie Mao; Guangyu Sun 003; Yong Li 009; Alex K. Jones; Yiran Chen 001 (ASP-DAC, 2014)

A Practical Data Classification Framework for Scalable and High Performance Chip-Multiprocessors. - Yong Li 009; Rami G. Melhem; Alex K. Jones (IEEE Trans. Computers, 2014)

Multilane Racetrack caches: Improving efficiency through compression and independent shifting. - Haifeng Xu; Yong Li 009; Rami G. Melhem; Alex K. Jones (ASP-DAC, 2015)

Space Oblivious Compression: Power Reduction for Non-Volatile Main Memories. - Yong Li 009; Haifeng Xu; Rami G. Melhem; Alex K. Jones (ACM Great Lakes Symposium on VLSI, 2015)

Improving efficiency of wireless sensor networks through lightweight in-memory compression. - Haifeng Xu; Yong Li 009; William O. Collinge; Laura A. Schaefer; Melissa M. Bilec; Alex K. Jones; Amy E. Landis (IGSC, 2015)

Read Performance: The Newest Barrier in Scaled STT-RAM. - Yaojun Zhang; Yong Li 009; Zhenyu Sun 001; Hai Li 001; Yiran Chen 001; Alex K. Jones (IEEE Trans. Very Large Scale Integr. Syst., 2015)