Yong Liu

According to our database1, Yong Liu authored at least 19 papers between 2002 and 2016.

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Bibliography

2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.
IEEE J. Solid State Circuits, 2012

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS.
IEEE J. Solid State Circuits, 2012

A compact low-power 3D I/O in 45nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Solid-state and biological systems interface.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009
CMOS RF Biosensor Utilizing Nuclear Magnetic Resonance.
IEEE J. Solid State Circuits, 2009

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS.
IEEE J. Solid State Circuits, 2009

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Fast-Lock Hybrid PLL Combining Fractional-N and Integer-N Modes of Differing Bandwidths.
IEEE J. Solid State Circuits, 2008

CMOS Mini Nuclear Magnetic Resonance System and its Application for Biomolecular Sensing.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2002
A Flexible Embedded SRAM Compiler.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002


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