A Flexible Embedded SRAM Compiler. - Yong Liu 023; Zhiqiang Gao; Xiangqing He (DELTA, 2002)

IC/microfluidic hybrid system for magnetic manipulation of biological cells. - Hakho Lee; Yong Liu 023; Robert M. Westervelt; Donhee Ham (IEEE J. Solid State Circuits, 2006)

All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs. - Yong Liu 023; Woogeun Rhee; Daniel J. Friedman; Donhee Ham (ISSCC, 2007)

CMOS Mini Nuclear Magnetic Resonance System and its Application for Biomolecular Sensing. - Yong Liu 023; Nan Sun 003; Hakho Lee; Ralph Weissleder; Donhee Ham (ISSCC, 2008)

Fast-Lock Hybrid PLL Combining Fractional-N and Integer-N Modes of Differing Bandwidths. - Kyoungho Woo; Yong Liu 023; Eunsoo Nam; Donhee Ham (IEEE J. Solid State Circuits, 2008)

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS. - Yong Liu 023; Byungsub Kim; Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (ISSCC, 2009)

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS. - Byungsub Kim; Yong Liu 023; Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2009)

CMOS RF Biosensor Utilizing Nuclear Magnetic Resonance. - Nan Sun 003; Yong Liu 023; Hakho Lee; Ralph Weissleder; Donhee Ham (IEEE J. Solid State Circuits, 2009)

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. - Jae-sun Seo; Bernard Brezzo; Yong Liu 023; Benjamin D. Parker; Steven K. Esser; Robert K. Montoye; Bipin Rajendran; José A. Tierno; Leland Chang; Dharmendra S. Modha; Daniel J. Friedman (CICC, 2011)

Solid-state and biological systems interface. - Nan Sun 003; Yong Liu 023; Ling Qin; Guangyu Xu; Donhee Ham (ESSCIRC, 2012)

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. - Ankur Agrawal; John F. Bulzacchelli; Timothy O. Dickson; Yong Liu 023; José A. Tierno; Daniel J. Friedman (ISSCC, 2012)

A compact low-power 3D I/O in 45nm CMOS. - Yong Liu 023; Wing K. Luk; Daniel J. Friedman (ISSCC, 2012)

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS. - Ankur Agrawal; John F. Bulzacchelli; Timothy O. Dickson; Yong Liu 023; José A. Tierno; Daniel J. Friedman (IEEE J. Solid State Circuits, 2012)

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Bing Dang; Cornelia K. Tsang; Paul S. Andry; John F. Bulzacchelli; Herschel A. Ainspan; Xiaoxiong Gu; Lavanya Turlapati; Michael P. Beakes; Benjamin D. Parker; et al. (IEEE J. Solid State Circuits, 2012)

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. - Yong Liu 023; Ping-Hsuan Hsieh; Seongwon Kim; Jae-sun Seo; Robert K. Montoye; Leland Chang; José A. Tierno; Daniel J. Friedman (ISSCC, 2013)

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Christian W. Baks; et al. (CICC, 2014)

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. - Timothy O. Dickson; Yong Liu 023; Ankur Agrawal; John F. Bulzacchelli; Herschel A. Ainspan; Zeynep Toprak Deniz; Benjamin D. Parker; Mounir Meghelli; Daniel J. Friedman (CICC, 2015)

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; et al. (IEEE J. Solid State Circuits, 2015)

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. - Sergey V. Rylov; Troy J. Beukema; Zeynep Toprak Deniz; Thomas Toifl; Yong Liu 023; Ankur Agrawal; Peter Buchmann; Alexander V. Rylyakov; Michael P. Beakes; Benjamin D. Parker; Mounir Meghelli (ISSCC, 2016)

A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. - Timothy O. Dickson; Yong Liu 023; Ankur Agrawal; John F. Bulzacchelli; Herschel A. Ainspan; Zeynep Toprak Deniz; Benjamin D. Parker; Michael P. Beakes; Mounir Meghelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2016)