26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique. - Hyeok-Ki Hong; Hyun-Wook Kang; Dong-Shin Jo; Dong-Suk Lee; Yong-Sang You; Yong-Hee Lee; Ho-Jin Park; Seung-Tak Ryu (ISSCC, 2015)

26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS. - Ba-Ro-Saim Sung; Dong-Shin Jo; Il-Hoon Jang; Dong-Suk Lee; Yong-Sang You; Yong-Hee Lee; Ho-Jin Park; Seung-Tak Ryu (ISSCC, 2015)