A mixed-structure delay locked-loop with wide range and fast locking. - Youngkwon Jo; Yong Shim; Soo Hwan Kim; Suki Kim; Kwanjun Cho (ISCAS, 2006)

A register controlled delay locked loop using a TDC and a new fine delay line scheme. - Yong Shim; Youngkwon Jo; Soo Hwan Kim; Suki Kim; Kwanjun Cho (ISCAS, 2006)

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. - Kyomin Sohn; Taesik Na; Indal Song; Yong Shim; Wonil Bae; Sanghee Kang; Dongsu Lee; Hangyun Jung; Hanki Jeoung; Ki Won Lee; Junsuk Park; Jongeun Lee; et al. (ISSCC, 2012)

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme. - Kyomin Sohn; Taesik Na; Indal Song; Yong Shim; Wonil Bae; Sanghee Kang; Dongsu Lee; Hangyun Jung; Seok-Hun Hyun; Hanki Jeoung; Ki Won Lee; Jun-Seok Park; et al. (IEEE J. Solid State Circuits, 2013)

STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks. - Deliang Fan; Yong Shim; Anand Raghunathan; Kaushik Roy 001 (CoRR, 2014)

Simulation studies of an All-Spin Artificial Neural Network: Emulating neural and synaptic functionalities through domain wall motion in ferromagnets. - Abhronil Sengupta; Yong Shim; Kaushik Roy 001 (CoRR, 2015)

Computing with coupled Spin Torque Nano Oscillators. - Karthik Yogendra; Deliang Fan; Yong Shim; Minsuk Koo; Kaushik Roy 001 (ASP-DAC, 2016)

Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications. - Yong Shim; Abhronil Sengupta; Kaushik Roy 001 (DAC, 2016)

Ising spin model using Spin-Hall Effect (SHE) induced magnetization reversal in Magnetic-Tunnel-Junction. - Yong Shim; Akhilesh Jaiswal 001; Kaushik Roy 001 (CoRR, 2016)

Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets. - Abhronil Sengupta; Yong Shim; Kaushik Roy 001 (IEEE Trans. Biomed. Circuits Syst., 2016)

Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization. - Yong Shim; Akhilesh Jaiswal 001; Kaushik Roy 001 (ICCD, 2017)

Stochastic Spin-Orbit Torque Devices as Elements for Bayesian Inference. - Yong Shim; Shuhan Chen; Abhronil Sengupta; Kaushik Roy 001 (CoRR, 2017)

Coupled Spin-Torque Nano-Oscillator-Based Computation: A Simulation Study. - Karthik Yogendra; Chamika M. Liyanagedera; Deliang Fan; Yong Shim; Kaushik Roy 001 (ACM J. Emerg. Technol. Comput. Syst., 2017)

Stochastic Algorithms for Optimization: Devices, Circuits, and Architecture - Yong Shim (2018)

sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network With On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge. - Minsuk Koo; Gopalakrishnan Srinivasan; Yong Shim; Kaushik Roy 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies. - Amogh Agrawal; Indranil Chakraborty; Deboleena Roy; Utkarsh Saxena; Saima Sharmin; Minsuk Koo; Yong Shim; Gopalakrishnan Srinivasan; Chamika M. Liyanagedera; Abhronil Sengupta; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

An Accurate Time-Based MPPT Circuit With Two-Period Tracking Algorithm and Convergence Range Averaging Technique for IoT Applications. - Van-Thai Dang; Myeong-Gyu Yang; Yong Shim; Woojoo Lee; Kwang-Hyun Baek (IEEE Access, 2021)

A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator. - Jae-Soub Han; Tae-Hyeok Eom; Seong-Wook Choi; Kiho Seong; Dong-Hyun Yoon; Tony Tae-Hyoung Kim; Kwang-Hyun Baek; Yong Shim (Sensors, 2021)

A Highly Efficient Time-Based MPPT Circuit With Extended Power Range and Minimized Tuning Switching Frequency. - Van-Thai Dang; Myeong-Gyu Yang; Chung-Hee Jang; Sukho Lee; Yong Shim; Kwang-Hyun Baek (IEEE Access, 2022)

A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator. - Dong-Kyu Jung; Kiho Seong; Jae-Soub Han; Yong Shim; Kwang-Hyun Baek (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 2.5 GS/s 7-Bit 5-Way Time-Interleaved SAR ADC With On-Chip Background Offset and Timing-Skew Calibration. - Kiho Seong; Jae-Soub Han; Yong Shim; Kwang-Hyun Baek (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Coupled 7T 1C SRAM based in-memory computing architecture with gain/offset error auto-compensated SAR ADC. - Honggu Kim; Yerim An; Yong Shim (ISLPED, 2024)

8T-SRAM Based Process-In-Memory (PIM) System With Current Mirror for Accurate MAC Operation. - Keun-Yong Chung; Honggu Kim; Yerim An; Kiho Seong; Dong-Hyun Shin; Kwang-Hyun Baek; Yong Shim (IEEE Access, 2024)

Union SRAM: PVT Variation Auto-Compensated, Bit Precision Configurable Current Mode 8T SRAM in Memory MAC Macro. - Honggu Kim; Yerim An; Ryunyeong Kim; Sunyoung Kim; Yong Shim (IEEE Access, 2024)

Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC Operations. - Yerim An; Honggu Kim; Dongjun Son; Hakrae Yu; Yong Shim (IEEE Access, 2025)

All Stochastic-Spiking Neural Network (AS-SNN): Noise Induced Spike Pulse Generator for Input and Output Neurons With Resistive Synaptic Array. - Honggu Kim; Yerim An; Minchul Kim; Gyeong-Chan Heo; Yong Shim (IEEE Trans. Circuits Syst. II Express Briefs, 2025)