ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction. - Minsik Cho; Kun Yuan 002; Yongchan Ban; David Z. Pan (DAC, 2008)

Double patterning technology friendly detailed routing. - Minsik Cho; Yongchan Ban; David Z. Pan (ICCAD, 2008)

ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction. - Minsik Cho; Kun Yuan 002; Yongchan Ban; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography. - Yongchan Ban; David Z. Pan (DAC, 2010)

Total sensitivity based dfm optimization of standard library cells. - Yongchan Ban; Savithri Sundareswaran; David Z. Pan (ISPD, 2010)

Flexible 2D layout decomposition framework for spacer-type double pattering lithography. - Yongchan Ban; Kevin Lucas; David Z. Pan (DAC, 2011)

Layout aware line-edge roughness modeling and poly optimization for leakage minimization. - Yongchan Ban; Jae-Seok Yang (DAC, 2011)

Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. - Yen-Hung Lin; Yongchan Ban; David Z. Pan; Yih-Lang Li (ICCAD, 2011)

Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization. - Yongchan Ban; David Z. Pan (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). - Bei Yu 001; Jhih-Rong Gao; Duo Ding; Yongchan Ban; Jae-Seok Yang; Kun Yuan 002; Minsik Cho; David Z. Pan (ICCAD, 2012)

Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line. - Wei Ye 008; Bei Yu 001; David Z. Pan; Yongchan Ban; Lars Liebmann (ACM Great Lakes Symposium on VLSI, 2015)