Novel bootstrapped CMOS differential logic family for ultra-low voltage SoCs. - Byung Hwa Jung; Sung-Chan Kang; Jae-Hyuk Oh; Yoon-Suk Park; Yong-Ki Kim 002; Yonggu Kang; Jong-Woo Kim; Bai-Sun Kong (IEICE Electron. Express, 2008)

CMOS cross-coupled charge pump with improved latch-up immunity. - Su-Jin Park; Yonggu Kang; Joung-Yeal Kim; Tae Hee Han; Young-Hyun Jun; Chil-Gee Lee; Bai-Sun Kong (IEICE Electron. Express, 2009)

A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. - Kibong Koo; Sunghwa Ok; Yonggu Kang; Seungbong Kim; Choungki Song; Hyeyoung Lee; Hyungsoo Kim; Yongmi Kim; Jeonghun Lee; Seunghan Oak; Yosep Lee; Jungyu Lee 002; et al. (ISSCC, 2012)

25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. - Hyun-Woo Lee; Junyoung Song; Sangah Hyun; Seunggeun Baek; Yuri Lim; Jungwan Lee; Minsu Park; Haerang Choi; Changkyu Choi; Jin-Youp Cha; Jaeil Kim; Hoon Choi; et al. (ISSCC, 2014)