Analysis of how to use the GEB developing. - Na Wei; Yongliang Zhou (ICEE, 2010)

Rank-two residue iteration method for nonnegative matrix factorization. - Hongwei Liu 001; Yongliang Zhou (Neurocomputing, 2011)

Robust activating timing for SRAM SA with replica cell voltage boosted circuit. - Zhengping Li; Mingming Xie; Xincun Ji; Yongliang Zhou (IEICE Electron. Express, 2016)

A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement. - Yongliang Zhou; Menglin Han; Mingyue Liu; Hao Cai 001; Bo Liu 019; Jun Yang 006 (NANOARCH, 2019)

Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing. - Hao Cai 001; Honglan Jiang; Yongliang Zhou; Menglin Han; Bo Liu 019 (CCF Trans. High Perform. Comput., 2020)

Magnetic Tunnel Junction Applications. - Nilson Maciel; Elaine Crespo Marques; Lirida A. B. Naviner; Yongliang Zhou; Hao Cai 001 (Sensors, 2020)

MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing. - Yongliang Zhou; Hao Cai 001; Bo Liu 019; Weisheng Zhao; Jun Yang 006 (IEEE Trans. Circuits Syst., 2020)

A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM. - Yongliang Zhou; Hao Cai 001; Lei Xie; Menglin Han; Mingyue Liu; Shi Xu; Bo Liu 019; Weisheng Zhao; Jun Yang 006 (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Challenge and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge Devices. - Xin Si; Yongliang Zhou; Jun Yang 006; Meng-Fan Chang (ASICON, 2021)

Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices. - Tianzhu Xiong; Yongliang Zhou; Yuyao Kong; Bo Wang 023; An Guo 001; Yufei Wang; Chen Xue; Haiming Hsu; Xin Si; Jun Yang 006 (ISOCC, 2021)

Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices. - Yufei Wang; Yongliang Zhou; Bo Wang 023; Tianzhu Xiong; Yuyao Kong; Xin Si (UCET, 2021)

A survey of in-spin transfer torque MRAM computing. - Hao Cai 001; Bo Liu 019; Juntong Chen; Lirida A. B. Naviner; Yongliang Zhou; Zhen Wang 019; Jun Yang 006 (Sci. China Inf. Sci., 2021)

Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration. - Hao Cai 001; Juntong Chen; Yongliang Zhou; Weisheng Zhao (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators. - Yongliang Zhou; Zuo Cheng; Han Liu; Tianzhu Xiong; Bo Wang (APCCAS, 2022)

ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations. - An Guo 001; Yongliang Zhou; Bo Wang 023; Tianzhu Xiong; Chen Xue; Yufei Wang; Xin Si; Jun Yang 006 (ISCAS, 2022)

SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. - Bo Wang 023; Chen Xue; Han Liu; Xiang Li; Anran Yin; Zhongyuan Feng; Yuyao Kong; Tianzhu Xiong; Haiming Hsu; Yongliang Zhou; An Guo 001; Yufei Wang; et al. (ISCAS, 2022)

Writing-only in-MRAM computing paradigm for ultra-low power applications. - Bo Liu 019; Mingyue Liu; Yongliang Zhou; Xiaofeng Hong; Hao Cai 001; Lirida Alves de Barros Naviner (Microprocess. Microsystems, 2022)

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. - Hao Cai 001; Zhongjian Bian; Yaoru Hou; Yongliang Zhou; Jia-Le Cui; Yanan Guo 004; Xiaoyun Tian; Bo Liu 019; Xin Si; Zhen Wang 019; Jun Yang 006; Weiwei Shan (ISSCC, 2023)

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Xin Si; Xi Chen 107; Fangyuan Dong; Xingyu Pu; Dongqi Li; Yongliang Zhou; Lizheng Ren; Yeyang Xue; Xueshan Dong; Hui Gao; Yiran Zhang; et al. (ISSCC, 2023)

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. - Bo Wang 023; Chen Xue; Zhongyuan Feng; Zhaoyang Zhang; Han Liu; Lizheng Ren; Xiang Li; Anran Yin; Tianzhu Xiong; Yeyang Xue; Shengnan He; Yuyao Kong; et al. (ISSCC, 2023)

A Single-Ended Offset-Canceling Sense Amplifier Enabling Wide-Voltage Operations. - Shan Shen; Hao Xu; Yongliang Zhou; Wenjian Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM. - Yongliang Zhou; Zhen Yang; Yiming Wei; Xiao Lin; Saiai Wu; Wenjuan Lu; Chunyu Peng; Xin Li 099; Xiulong Wu (ISCAS, 2024)

Ultra8T: A sub-threshold 8T SRAM with leakage detection. - Shan Shen; Hao Xu; Yongliang Zhou; Ming Ling; Wenjian Yu (Integr., 2024)

Configurable in-memory computing architecture based on dual-port SRAM. - Yue Zhao; Yunlong Liu; Jian Zheng; Zhongzhen Tong; Xin Wang; Runru Yu; Xiulong Wu; Yongliang Zhou; Chunyu Peng; Wenjuan Lu; Qiang Zhao 007; Zhiting Lin (Microelectron. J., 2024)

An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices. - Yongliang Zhou; Yiming Wei; Tianzhu Xiong; Zixuan Zhou; Zhen Yang; Xiao Lin; Wei Hu; Xiulong Wu; Chunyu Peng (Microelectron. J., 2024)

A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices. - Yongliang Zhou; Zixuan Zhou; Yiming Wei; Zhen Yang; Xiao Lin; Chenghu Dai; Licai Hao; Chunyu Peng; Hao Cai 001; Xiulong Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies. - Licai Hao; Xinyi Zhang; Chenghu Dai; Qiang Zhao 007; Wenjuan Lu; Chunyu Peng; Yongliang Zhou; Zhiting Lin; Xiulong Wu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design. - Licai Hao; Yaling Wang; Yunlong Liu; Shiyu Zhao; Xinyi Zhang; Yang Li; Wenjuan Lu; Chunyu Peng; Qiang Zhao 007; Yongliang Zhou; Chenghu Dai; Zhiting Lin; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense. - Yongliang Zhou; Xiao Lin; Zixuan Zhou; Yingxue Sun; Yiming Wei; Zhen Yang; Chengxing Dai; Jingxue Zhong; Xiulong Wu; Chunyu Peng (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

MTJ based temperature compensated beta multiplier Voltage Reference. - Yongliang Zhou; Yingxue Sun; Jingxue Zhong; Chengxing Dai; Weizhe Tan; Chunyu Peng; Xin Li 099; Zhigang Li; Zhiting Lin; Xiulong Wu (ISCAS, 2025)

MTJ based Temperature-Adaptive VCO (TAVCO) for Compensating CP-PLL Frequency Drift. - Yongliang Zhou; Jingxue Zhong; Yingxue Sun; Chengxing Dai; Weizhe Tan; Chunyu Peng; Wenjuan Lu; Xin Li 099; Zhiting Lin; Xiulong Wu (ISCAS, 2025)

A high charge-discharge stability SRAM 10T1C XOR CIM macro applied in BCAM and Hamming distance. - Li Liu 004; Wei Hu; Zhen Yang; Yiming Wei; Chunyu Peng; Xiulong Wu; Zhiting Lin; Wenjuan Lu; Yongliang Zhou; Junning Chen (Microelectron. J., 2025)

Full-Array Boolean Logic CIM Macro With Self-Recycling 10T-SRAM Cell for AES Systems. - Xin Li 099; Ying Pan; Qian Jin; Lintao Chen; Yang Lou; Baofa Wu; Jiajun Long; Yongliang Zhou; Chunyu Peng; Xiulong Wu; Zhiting Lin (IEEE Trans. Very Large Scale Integr. Syst., 2025)