A Hierarchical Approach for Incremental Floorplan Based on Genetic Algorithms. - Yongpan Liu; Huazhong Yang; Rong Luo; Hui Wang 004 (ICNC (3), 2005)

A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection. - Yongpan Liu; Yu Wang 002; Feng Zhang 014; Rong Luo; Hui Wang 004 (APCCAS, 2006)

Techniques of Power-gating to Kill Sub-Threshold Leakage. - Changbo Long; Jinjun Xiong; Yongpan Liu (APCCAS, 2006)

Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization. - Yu Wang 002; Yongpan Liu; Rong Luo; Huazhong Yang (ICNC (1), 2006)

Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits. - Yu Wang 002; Yongpan Liu; Rong Luo; Huazhong Yang; Hui Wang 004 (ISLPED, 2006)

Accurate temperature-dependent integrated circuit leakage power estimation is easy. - Yongpan Liu; Robert P. Dick; Li Shang; Huazhong Yang (DATE, 2007)

A Hybrid Genetic Algorithm with Critical Primary Inputs Sharing and Minor Primary Inputs Bits Climbing for Circuit Maximum Power Estimation. - Zhixin Tian; Yongpan Liu; Huazhong Yang; Hui Wang 004 (ICNC (4), 2007)

Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems. - Yongpan Liu; Huazhong Yang; Robert P. Dick; Hui Wang 004; Li Shang (ISQED, 2007)

Energy-efficient spatially-adaptive clustering and routing in wireless sensor networks. - Hengyu Long; Yongpan Liu; Xiaoguang Fan; Robert P. Dick; Huazhong Yang (DATE, 2009)

Energy efficient architecture of sensor network node based on compression accelerator. - Jue Wang; Beihua Ying; Yongpan Liu; Huazhong Yang; Hui Wang 004 (ACM Great Lakes Symposium on VLSI, 2009)

Battery allocation for wireless sensor network lifetime maximization under cost constraints. - Hengyu Long; Yongpan Liu; Yiqun Wang; Robert P. Dick; Huazhong Yang (ICCAD, 2009)

Design methodology of variable latency adders with multistage function speculation. - Yongpan Liu; Yinan Sun; Yihao Zhu; Huazhong Yang (ISQED, 2010)

Lightweight Precision-Adaptive Time Synchronization in Wireless Sensor Networks. - Li Li; Yongpan Liu; Huazhong Yang; Hui Wang 004 (IEICE Trans. Commun., 2010)

Temperature-Aware Leakage Estimation Using Piecewise Linear Power Models. - Yongpan Liu; Huazhong Yang (IEICE Trans. Electron., 2010)

Evaluation of Tunable Data Compression in Energy-Aware Wireless Sensor Networks. - Beihua Ying; Yongpan Liu; Huazhong Yang; Hui Wang 004 (Sensors, 2010)

Design methodology of multistage time-domain logic speculation circuits. - Yinan Sun; Yongpan Liu; Xiaohan Wang; Hongliang Xu; Huazhong Yang (ISCAS, 2011)

An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression. - Yongpan Liu; Shuangchen Li; Jue Wang; Beihua Ying; Huazhong Yang (IEICE Trans. Electron., 2011)

A hierarchical C2RTL framework for FIFO-connected stream applications. - Shuangchen Li; Yongpan Liu; Daming Zhang; Xinyu He; Pei Zhang; Huazhong Yang (ASP-DAC, 2012)

A compression-based area-efficient recovery architecture for nonvolatile processors. - Yiqun Wang; Yongpan Liu; Yumeng Liu; Daming Zhang; Shuangchen Li; Baiko Sai; Mei-Fang Chiang; Huazhong Yang (DATE, 2012)

A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops. - Yiqun Wang; Yongpan Liu; Shuangchen Li; Daming Zhang; Bo Zhao 003; Mei-Fang Chiang; Yanxin Yan; Baiko Sai; Huazhong Yang (ESSCIRC, 2012)

An energy harvesting nonvolatile sensor node and its application to distributed moving object detection. - Yongpan Liu; Yiqun Wang; Hongyang Jia; Shan Su; Jinghuan Wen; Wenzhu Zhang; Lin Zhang 001; Huazhong Yang (IPSN, 2012)

Utilizing PCM for Energy Optimization in Embedded Systems. - Zili Shao; Yongpan Liu; Yiran Chen 001; Tao Li 006 (ISVLSI, 2012)

A low-complexity symbol-level differential detection scheme for IEEE 802.15.4 O-QPSK signals. - Cong Wang; Yongpan Liu; Rong Luo; Huazhong Yang (WCSP, 2012)

Lifetime-Aware Battery Allocation for Wireless Sensor Network under Cost Constraints. - Yongpan Liu; Yiqun Wang; Hengyu Long; Huazhong Yang (IEICE Trans. Commun., 2012)

Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications. - Shuangchen Li; Yongpan Liu; Xiaobo Sharon Hu; Xinyu He; Yining Zhang; Pei Zhang; Huazhong Yang (ASP-DAC, 2013)

Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications. - Xinyu He; Shuangchen Li; Yongpan Liu; Xiaobo Sharon Hu; Huazhong Yang (DATE, 2013)

SPaC: a segment-based parallel compression for backup acceleration in nonvolatile processors. - Xiao Sheng; Yiqun Wang; Yongpan Liu; Huazhong Yang (DATE, 2013)

Storage-less and converter-less maximum power point tracking of photovoltaic cells for a nonvolatile microprocessor. - Cong Wang; Naehyuck Chang; Younghyun Kim 001; Sangyoung Park; Yongpan Liu; Hyung Gyu Lee; Rong Luo; Huazhong Yang (ASP-DAC, 2014)

Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodes. - Daming Zhang; Shuangchen Li; Ang Li 005; Yongpan Liu; Xiaobo Sharon Hu; Huazhong Yang (ICCD, 2014)

Register allocation for hybrid register architecture in nonvolatile processors. - Yiqun Wang; Hongyang Jia; Yongpan Liu; Qing'an Li; Chun Jason Xue; Huazhong Yang (ISCAS, 2014)

A high-efficiency dual-channel photovoltaic power system for nonvolatile sensor nodes. - Xiao Sheng; Cong Wang; Yongpan Liu; Hyung Gyu Lee; Naehyuck Chang; Huazhong Yang (NVMSA, 2014)

PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors. - Yiqun Wang; Yongpan Liu; Shuangchen Li; Xiao Sheng; Daming Zhang; Mei-Fang Chiang; Baiko Sai; Xiaobo Sharon Hu; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Nonvolatile memory allocation and hierarchy optimization for high-level synthesis. - Shuangchen Li; Ang Li 005; Yongpan Liu; Yuan Xie 001; Huazhong Yang (ASP-DAC, 2015)

Self-powered wearable sensor node: Challenges and opportunities. - Yongpan Liu; Hehe Li; Xueqing Li 002; Chun Jason Xue; Yuan Xie 001; Huazhong Yang (CASES, 2015)

A STT-RAM-based low-power hybrid register file for GPGPUs. - Gushu Li; Xiaoming Chen 003; Guangyu Sun 003; Henry Hoffmann; Yongpan Liu; Yu Wang 002; Huazhong Yang (DAC, 2015)

Compiler directed automatic stack trimming for efficient non-volatile processors. - Qing'an Li; Mengying Zhao; Jingtong Hu; Yongpan Liu; Yanxiang He; Chun Jason Xue (DAC, 2015)

Ambient energy harvesting nonvolatile processors: from circuit to system. - Yongpan Liu; Zewei Li; Hehe Li; Yiqun Wang; Xueqing Li 002; Kaisheng Ma; Shuangchen Li; Meng-Fan Chang; John Sampson; Yuan Xie 001; Jiwu Shu; Huazhong Yang (DAC, 2015)

Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor. - Mimi Xie; Mengying Zhao; Chen Pan; Jingtong Hu; Yongpan Liu; Chun Jason Xue (DAC, 2015)

Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration. - Daming Zhang; Yongpan Liu; Xiao Sheng; Jinyang Li 002; Tongda Wu; Chun Jason Xue; Huazhong Yang (DAC, 2015)

An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes. - Hehe Li; Yongpan Liu; Qinghang Zhao; Yizi Gu; Xiao Sheng; Guangyu Sun 003; Chao Zhang 007; Meng-Fan Chang; Rong Luo; Huazhong Yang (DATE, 2015)

From device to system: cross-layer design exploration of racetrack memory. - Guangyu Sun 003; Chao Zhang 007; Hehe Li; Yue Zhang 010; Weiqi Zhang; Yizi Gu; Yinan Sun; Jacques-Olivier Klein; Dafine Ravelosona; Yongpan Liu; Weisheng Zhao; Huazhong Yang (DATE, 2015)

Software assisted non-volatile register reduction for energy harvesting based cyber-physical system. - Mengying Zhao; Qing'an Li; Mimi Xie; Yongpan Liu; Jingtong Hu; Chun Jason Xue (DATE, 2015)

Multi-source energy harvesting management and optimization for non-volatile processors. - Soroush Heidari; Caiwen Ding; Yongpan Liu; Yanzhi Wang; Jingtong Hu (IGSC, 2015)

Architecture exploration for ambient energy harvesting nonvolatile processors. - Kaisheng Ma; Yang Zheng; Shuangchen Li; Karthik Swaminathan; Xueqing Li 002; Yongpan Liu; Jack Sampson; Yuan Xie 001; Vijaykrishnan Narayanan (HPCA, 2015)

Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile. - Kaisheng Ma; Xueqing Li 002; Yongpan Liu; John Sampson; Yuan Xie 001; Vijaykrishnan Narayanan (ICCAD, 2015)

Hi-fi playback: tolerating position errors in shift operations of racetrack memory. - Chao Zhang 007; Guangyu Sun 003; Xian Zhang 001; Weiqi Zhang; Weisheng Zhao; Tao Wang 004; Yun Liang 001; Yongpan Liu; Yu Wang 002; Jiwu Shu (ISCA, 2015)

An energy-efficient heterogeneous dual-core processor for Internet of Things. - Zhibo Wang 004; Yongpan Liu; Yinan Sun; Yang Li; Daming Zhang; Huazhong Yang (ISCAS, 2015)

Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations. - Shuangchen Li; Ang Li 005; Yuan Zhe; Yongpan Liu; Peng Li 001; Guangyu Sun 003; Yu Wang 002; Huazhong Yang; Yuan Xie 001 (ISLPED, 2015)

Design exploration of inrush current aware controller for nonvolatile processor. - Yongpan Liu; Fang Su; Zhibo Wang 004; Huazhong Yang (NVMSA, 2015)

Modular Performance Analysis of Energy-Harvesting Real-Time Networked Systems. - Nan Guan; Mengying Zhao; Chun Jason Xue; Yongpan Liu; Wang Yi 001 (RTSS, 2015)

Multistage Function Speculation Adders. - Yinan Sun; Yongpan Liu; Zhibo Wang 004; Huazhong Yang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications. - Kaisheng Ma; Xueqing Li 002; Shuangchen Li; Yongpan Liu; John (Jack) Morgan Sampson; Yuan Xie 001; Vijaykrishnan Narayanan (IEEE Micro, 2015)

NVPsim: A simulator for architecture explorations of nonvolatile processors. - Yizi Gu; Yongpan Liu; Yiqun Wang; Hehe Li; Huazhong Yang (ASP-DAC, 2016)

Performance-centric register file design for GPUs using racetrack memory. - Shuo Wang 009; Yun Liang 001; Chao Zhang 007; Xiaolong Xie; Guangyu Sun 003; Yongpan Liu; Yu Wang 002; Xiuhong Li (ASP-DAC, 2016)

CP-FPGA: Computation data-aware software/hardware co-design for nonvolatile FPGAs based on checkpointing techniques. - Zhe Yuan; Yongpan Liu; Hehe Li; Huazhong Yang (ASP-DAC, 2016)

Accurate personal ultraviolet dose estimation with multiple wearable sensors. - Jinyang Li 002; Yongpan Liu; Hehe Li; Rui Hua; Chun Jason Xue; Hyung Gyu Lee; Huazhong Yang (BSN, 2016)

Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems. - Mimi Xie; Mengying Zhao; Chen Pan; Hehe Li; Yongpan Liu; Youtao Zhang; Chun Jason Xue; Jingtong Hu (CODES+ISSS, 2016)

Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead. - Hehe Li; Yongpan Liu; Chenchen Fu; Chun Jason Xue; Donglai Xiang; Jinshan Yue; Jinyang Li 002; Daming Zhang; Jingtong Hu; Huazhong Yang (DAC, 2016)

HW/SW co-design of nonvolatile IO system in energy harvesting sensor nodes for optimal data acquisition. - Zewei Li; Yongpan Liu; Daming Zhang; Chun Jason Xue; Zhangyuan Wang; Xin Shi; Wenyu Sun; Jiwu Shu; Huazhong Yang (DAC, 2016)

Dynamic converter reconfiguration for near-threshold non-volatile processors using in-door energy harvesting. - Caiwen Ding; Hongjia Li; Jingtong Hu; Yongpan Liu; Yanzhi Wang (ICCD, 2016)

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. - Ping Chi; Shuangchen Li; Cong Xu 002; Tao Zhang 032; Jishen Zhao; Yongpan Liu; Yu Wang 002; Yuan Xie 001 (ISCA, 2016)

Multi-source in-door energy harvesting for non-volatile processors. - Caiwen Ding; Soroush Heidari; Yanzhi Wang; Yongpan Liu; Jingtong Hu (ISCAS, 2016)

SATS: An Ultra-Low Power Time Synchronization for Solar Energy Harvesting WSNs. - Tongda Wu; Yongpan Liu; Hehe Li; Chun Jason Xue; Hyung Gyu Lee; Huazhong Yang (ISLPED, 2016)

4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic. - Yongpan Liu; Zhibo Wang 004; Albert Lee; Fang Su; Chieh-Pu Lo; Zhe Yuan; Chien-Chen Lin; Qi Wei 001; Yu Wang 002; Ya-Chin King; Chrong Jung Lin; Pedram Khalili; et al. (ISSCC, 2016)

A compare-and-select error tolerant scheme for nonvolatile processors. - Zhibo Wang 004; Rui Hua; Yongpan Liu; Huazhong Yang (NANOARCH, 2016)

Design of nonvolatile processors and applications. - Fang Su; Zhibo Wang 004; Jinyang Li 002; Meng-Fan Chang; Yongpan Liu (VLSI-SoC, 2016)

Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power. - Kaisheng Ma; Xueqing Li 002; Karthik Swaminathan; Yang Zheng; Shuangchen Li; Yongpan Liu; Yuan Xie 001; John (Jack) Morgan Sampson; Vijaykrishnan Narayanan (IEEE Micro, 2016)

Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation. - Xiaoming Chen 003; Lin Wang; Boxun Li; Yu Wang 002; Xin Li 001; Yongpan Liu; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Storage-Less and Converter-Less Photovoltaic Energy Harvesting With Maximum Power Point Tracking for Internet of Things. - Yiqun Wang; Yongpan Liu; Cong Wang; Zewei Li; Xiao Sheng; Hyung Gyu Lee; Naehyuck Chang; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes. - Daming Zhang; Yongpan Liu; Jinyang Li 002; Chun Jason Xue; Xueqing Li 002; Yu Wang 002; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A Unified Methodology for Designing Hardware Random Number Generators Based on Any Probability Distribution. - Xiaoming Chen 003; Boxun Li; Yu Wang 002; Yongpan Liu; Huazhong Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Wear-Leveling Aware Page Management for Non-Volatile Main Memory on Embedded Systems. - Chen Pan; Shouzhen Gu; Mimi Xie; Yongpan Liu; Chun Jason Xue; Jingtong Hu (IEEE Trans. Multi Scale Comput. Syst., 2016)

A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications. - Daming Zhang; Shuangchen Li; Yongpan Liu; Xiaobo Sharon Hu; Xinyu He; Yining Zhang; Pei Zhang; Huazhong Yang (ACM Trans. Design Autom. Electr. Syst., 2016)

'The danger of sleeping', an exploration of security in non-volatile processors. - Patrick Cronin; Chengmo Yang; Dongqin Zhou; Keni Qiu; Xin Shi; Yongpan Liu (AsianHOST, 2017)

Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors. - Kaisheng Ma; Xueqing Li 002; Srivatsa Rangachar Srinivasa; Yongpan Liu; John Sampson; Yuan Xie 001; Vijaykrishnan Narayanan (ASP-DAC, 2017)

Retention state-aware energy management for efficient nonvolatile processors: work-in-progress. - Keni Qiu; Zhiyao Gong; Dongqin Zhou; Weiwen Chen; Yongpan Liu (CODES+ISSS, 2017)

Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture. - Qinghang Zhao; Yongpan Liu; Wenyu Sun; Jiaqing Zhao; Hailong Yao; Xiaojun Guo; Huazhong Yang (DAC, 2017)

Nonvolatile processors: Why is it trending? - Fang Su; Kaisheng Ma; Xueqing Li 002; Tongda Wu; Yongpan Liu; Vijaykrishnan Narayanan (DATE, 2017)

CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper). - Jinyang Li 002; Qingwei Guo; Fang Su; Zhe Yuan; Jinshan Yue; Jingtong Hu; Huazhong Yang; Yongpan Liu (ICCAD, 2017)

An 8b 0.8kS/s configurable VCO-based ADC using oxide TFTs with Inkjet printing interconnection. - Wenyu Sun; Qinghang Zhao; Fei Qiao; Yongpan Liu; Huazhong Yang; Xiaojun Guo; Lei Zhou; Lei Wang (ISCAS, 2017)

CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks. - Zhe Yuan; Yongpan Liu; Jinshan Yue; Jinyang Li 002; Huazhong Yang (ISLPED, 2017)

Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing. - Wei-Hao Chen; Win-San Khwa; Jun-Yi Li; Wei-Yu Lin; Huan-Ting Lin; Yongpan Liu; Yu Wang 002; Huaqiang Wu; Huazhong Yang; Meng-Fan Chang (ISQED, 2017)

A lightweight progress maximization scheduler for non-volatile processor under unstable energy harvesting. - Chen Pan; Mimi Xie; Yongpan Liu; Yanzhi Wang; Chun Jason Xue; Yuangang Wang; Yiran Chen 001; Jingtong Hu (LCTES, 2017)

Incidental computing on IoT nonvolatile processors. - Kaisheng Ma; Xueqing Li 002; Jinyang Li 002; Yongpan Liu; Yuan Xie 001; Jack Sampson; Mahmut Taylan Kandemir; Vijaykrishnan Narayanan (MICRO, 2017)

Retention state-enabled and progress-driven energy management for self-powered nonvolatile processors. - Zhiyao Gong; Keni Qiu; Dongqin Zhou; Weiwen Chen; Yuanchao Xu 002; Xin Shi; Yongpan Liu (RTCSA, 2017)

Multisource Indoor Energy Harvesting for Nonvolatile Processors. - Caiwen Ding; Ning Liu 007; Yanzhi Wang; Ji Li 006; Soroush Heidari; Jingtong Hu; Yongpan Liu (IEEE Des. Test, 2017)

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors. - Albert Lee; Chieh-Pu Lo; Chien-Chen Lin; Wei-Hao Chen; Kuo-Hsiang Hsu; Zhibo Wang 004; Fang Su; Zhe Yuan; Qi Wei 001; Ya-Chin King; Chrong Jung Lin; Hochul Lee; et al. (IEEE J. Solid State Circuits, 2017)

A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed. - Zhibo Wang 004; Yongpan Liu; Albert Lee; Fang Su; Chieh-Pu Lo; Zhe Yuan; Jinyang Li 002; Chien-Chen Lin; Wei-Hao Chen; Hsiao-Yun Chiu; Wei-En Lin; Ya-Chin King; et al. (IEEE J. Solid State Circuits, 2017)

A General Framework for Hardware Trojan Detection in Digital Circuits by Statistical Learning Algorithms. - Xiaoming Chen 003; Lin Wang; Yu Wang 002; Yongpan Liu; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes. - Yongpan Liu; Jinshan Yue; Hehe Li; Qinghang Zhao; Mengying Zhao; Chun Jason Xue; Guangyu Sun 003; Meng-Fan Chang; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors. - Mengying Zhao; Chenchen Fu; Zewei Li; Qing'an Li; Mimi Xie; Yongpan Liu; Jingtong Hu; Zhiping Jia; Chun Jason Xue (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops. - Xueqing Li 002; Sumitha George; Kaisheng Ma; Wei-Yu Tsai; Ahmedullah Aziz; John Sampson; Sumeet Kumar Gupta; Meng-Fan Chang; Yongpan Liu; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Ferroelectric Nonvolatile Processor with 46 $ mu $ s System-Level Wake-up Time and 14 $ mu $ s Sleep Time for Energy Harvesting Applications. - Fang Su; Yongpan Liu; Yiqun Wang; Huazhong Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Maximum Energy Efficiency Tracking Circuits for Converter-Less Energy Harvesting Sensor Nodes. - Yinan Sun; Zhe Yuan; Yongpan Liu; Xueqing Li 002; Yu Wang 002; Qi Wei 001; Yiqun Wang; Vijaykrishnan Narayanan; Huazhong Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems. - Kaisheng Ma; Xueqing Li 002; Huichu Liu; Xiao Sheng; Yiqun Wang; Karthik Swaminathan; Yongpan Liu; Yuan Xie 001; John Sampson; Vijaykrishnan Narayanan (ACM Trans. Embed. Comput. Syst., 2017)

DVFS-Based Long-Term Task Scheduling for Dual-Channel Solar-Powered Sensor Nodes. - Tongda Wu; Yongpan Liu; Daming Zhang; Jinyang Li 002; Xiaobo Sharon Hu; Chun Jason Xue; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

CP-FPGA: Energy-Efficient Nonvolatile FPGA With Offline/Online Checkpointing Optimization. - Zhe Yuan; Yongpan Liu; Jinyang Li 002; Jingtong Hu; Chun Jason Xue; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Mechanical strain and temperature aware design methodology for thin-film transistor based pseudo-CMOS logic array. - Wenyu Sun; Yuxuan Huang; Qinghang Zhao; Fei Qiao; Tsung-Yi Ho; Xiaojun Guo; Huazhong Yang; Yongpan Liu (ASP-DAC, 2018)

NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing. - Kaisheng Ma; Xueqing Li 002; Mahmut Taylan Kandemir; Jack Sampson; Vijaykrishnan Narayanan; Jinyang Li 002; Tongda Wu; Zhibo Wang 004; Yongpan Liu; Yuan Xie 001 (ASPLOS, 2018)

An Investigation on Inter-degeneration Effect in Body Channel Based Multi-node Wireless Power Transfer. - Yuxuan Huang; Jian Zhao 004; Wenyu Sun; Jingna Mao; Huazhong Yang; Yongpan Liu (BioCAS, 2018)

Dual-threshold directed execution progress maximization for nonvolatile processors. - Dongqin Zhou; Keni Qiu; Xin Shi; Yongpan Liu (CF, 2018)

A collaborative defense against wear out attacks in non-volatile processors. - Patrick Cronin; Chengmo Yang; Yongpan Liu (DAC, 2018)

Live Demonstration: A self-powered ultraviolet radiation monitoring platform based on nonvolatile processor. - Xin Shi; Yongpan Liu; Yinan Sun; Yixiong Yang; Keni Qiu (ISCAS, 2018)

A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation. - Yixiong Yang; Zhibo Wang 004; Pei Yang; Meng-Fan Chang; Mon-Shu Ho; Huazhong Yang; Yongpan Liu (ISCAS, 2018)

Reliability and Security in Non-volatile Processors, Two Sides of the Same Coin. - Patrick Cronin; Chengmo Yang; Yongpan Liu (ISVLSI, 2018)

Time Stamp Based Scheduling for Energy Harvesting Systems with Hybrid Nonvolatile Hardware Support. - Xin Shi; Tongda Wu; Keni Qiu; Huazhong Yang; Yongpan Liu (ISVLSI, 2018)

Low Overhead Online Checkpoint for Intermittently Powered Non-volatile FPGAs. - Xinyi Zhang 001; Clay Patterson; Yongpan Liu; Chengmo Yang; Chun Jason Xue; Jingtong Hu (ISVLSI, 2018)

A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors. - Dongqin Zhou; Keni Qiu; Yuanchao Xu 002; Xin Shi; Yongpan Liu (ISVLSI, 2018)

Prototyping Energy Harvesting Powered Systems with Nonvolatile Processor (Invited Paper). - Yawen Wu; Yinan Sun; Zhenge Jia; Lefan Zhang; Yongpan Liu; Jingtong Hu (RSP, 2018)

An extensible system simulator for intermittently-powered multiple-peripheral IoT devices. - Tongda Wu; Lefan Zhang; Huazhong Yang; Yongpan Liu (ENSsys@SenSys, 2018)

Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers. - Zhe Yuan; Jinshan Yue; Huanrui Yang; Zhibo Wang 004; Jinyang Li 002; Yixiong Yang; Qingwei Guo; Xueqing Li 002; Meng-Fan Chang; Huazhong Yang; Yongpan Liu (VLSI Circuits, 2018)

Efficient energy management by exploiting retention state for self-powered nonvolatile processors. - Keni Qiu; Zhiyao Gong; Dongqin Zhou; Weiwen Chen; Yuanchao Xu 002; Xin Shi; Yongpan Liu (J. Syst. Archit., 2018)

IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors. - Kaisheng Ma; Jinyang Li 002; Xueqing Li 002; Yongpan Liu; Yuan Xie 001; Mahmut T. Kandemir; Jack Sampson; Vijaykrishnan Narayanan (IEEE Micro, 2018)

Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis. - Xiaoming Chen 003; Qiaoyi Liu; Song Yao; Jia Wang; Qiang Xu 001; Yu Wang 002; Yongpan Liu; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Avoiding Data Inconsistency in Energy Harvesting Powered Embedded Systems. - Mimi Xie; Chen Pan; Mengying Zhao; Yongpan Liu; Chun Jason Xue; Jingtong Hu (ACM Trans. Design Autom. Electr. Syst., 2018)

PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors. - Jinyang Li 002; Yongpan Liu; Hehe Li; Zhe Yuan; Chenchen Fu; Jinshan Yue; Xiaoyu Feng; Chun Jason Xue; Jingtong Hu; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Accelerating CNN-RNN Based Machine Health Monitoring on FPGA. - Xiaoyu Feng; Jinshan Yue; Qingwei Guo; Huazhong Yang; Yongpan Liu (AICAS, 2019)

An N-way group association architecture and sparse data group association load balancing algorithm for sparse CNN accelerators. - Jingyu Wang 004; Zhe Yuan; Ruoyang Liu; Huazhong Yang; Yongpan Liu (ASP-DAC, 2019)

AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip. - Jinshan Yue; Yongpan Liu; Fang Su; Shuangchen Li; Zhe Yuan; Zhibo Wang 004; Wenyu Sun; Xueqing Li 002; Huazhong Yang (ASP-DAC, 2019)

A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler. - Zhe Yuan; Jingyu Wang 004; Yixiong Yang; Jinshan Yue; Zhibo Wang 004; Xiaoyu Feng; Yanzhi Wang; Xueqing Li 002; Huazhong Yang; Yongpan Liu (A-SSCC, 2019)

A 4-Mbps 41-pJ/bit On-off Keying Transceiver for Body-channel Communication with Enhanced Auto Loss Compensation Technique. - Jian Zhao 004; Jingna Mao; Wenyu Sun; Yuxuan Huang; Yixiong Yang; Huazhong Yang; Yongpan Liu (A-SSCC, 2019)

A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs. - Juejian Wu; Hongtao Zhong; Kai Ni 004; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (DAC, 2019)

A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture. - Jinshan Yue; Ruoyang Liu; Wenyu Sun; Zhe Yuan; Zhibo Wang 004; Yung-Ning Tu; Yi-Ju Chen; Ao Ren; Yanzhi Wang; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang; et al. (ISSCC, 2019)

Flexible Circuits and Systems for Smart Biomedical Applications. - Yongpan Liu (VLSI-DAT, 2019)

Progressive DNN Compression: A Key to Achieve Ultra-High Weight Pruning and Quantization Rates using ADMM. - Shaokai Ye; Xiaoyu Feng; Tianyun Zhang; Xiaolong Ma; Sheng Lin 001; Zhengang Li; Kaidi Xu; Wujie Wen; Sijia Liu 001; Jian Tang 008; Makan Fardad; Xue Lin 001; et al. (CoRR, 2019)

A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond. - Qiang Huo; Zhenhua Wu; Weixing Huang; Xingsheng Wang; Geyu Tang; Jiaxin Yao; Yongpan Liu; Feng Zhang 014; Ling Li 013; Ming Liu 022 (CoRR, 2019)

Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs. - Xueqing Li 002; Juejian Wu; Kai Ni 004; Sumitha George; Kaisheng Ma; John Sampson; Sumeet Kumar Gupta; Yongpan Liu; Huazhong Yang; Suman Datta; Vijaykrishnan Narayanan (IEEE Des. Test, 2019)

A global and updatable ECG beat classification system based on recurrent neural networks and active learning. - Guijin Wang; Chenshuang Zhang; Yongpan Liu; Huazhong Yang; Dapeng Fu; Haiqing Wang; Ping Zhang (Inf. Sci., 2019)

A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System. - Yongpan Liu; Fang Su; Yixiong Yang; Zhibo Wang 004; Yiqun Wang; Zewei Li; Xueqing Li 002; Ryuji Yoshimura; Takashi Naiki; Takashi Tsuwa; Takahiko Saito; Zhongjun Wang; et al. (IEEE J. Solid State Circuits, 2019)

A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices. - Mimi Xie; Chen Pan; Youtao Zhang; Jingtong Hu; Yongpan Liu; Chun Jason Xue (IEEE Micro, 2019)

Dynamic Channel Modeling and OFDM System Analysis for Capacitive Coupling Body Channel Communication. - Wenyu Sun; Jian Zhao 004; Yuxuan Huang; Yinan Sun; Huazhong Yang; Yongpan Liu (IEEE Trans. Biomed. Circuits Syst., 2019)

An Auto Loss Co Jian Zhaompensation System for Capacitive-Coupled Body Channel Communication. - Jian Zhao 004; Wenyu Sun; Jingna Mao; Yuxuan Huang; Bo Zhao 003; Yongpan Liu; Huazhong Yang (IEEE Trans. Biomed. Circuits Syst., 2019)

GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing. - Guohao Dai; Tianhao Huang; Yuze Chi; Jishen Zhao; Guangyu Sun 003; Yongpan Liu; Yu Wang 002; Yuan Xie 001; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile Processors. - Fuyang Li; Keni Qiu; Mengying Zhao; Jingtong Hu; Yongpan Liu; Yong Guan; Chun Jason Xue (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms. - Qinghang Zhao; Wenyu Sun; Jiaqing Zhao; Jian Zhao 004; Hailong Yao; Tsung-Yi Ho; Xiaojun Guo; Huazhong Yang; Yongpan Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs. - Longqiang Lai; Xueqing Li 002; Yushen Fu; Yongpan Liu; Huazhong Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation. - Yixiong Yang; Xin Shi; Fang Su; Zhibo Wang 004; Pei Yang; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization. - Jinshan Yue; Yongpan Liu; Zhe Yuan; Zhibo Wang 004; Qingwei Guo; Jinyang Li 002; Chengmo Yang; Huazhong Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Task Failure Rate Aware Dual-Channel Solar Power System for Nonvolatile Sensor Nodes. - Fang Su; Yongpan Liu; Xiao Sheng; Hyung Gyu Lee; Naehyuck Chang; Huazhong Yang (ACM Trans. Embed. Comput. Syst., 2019)

Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory. - Juejian Wu; Yixin Xu 001; Bowen Xue; Yu Wang 002; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ASP-DAC, 2020)

A 112-765 GOPS/W FPGA-based CNN Accelerator using Importance Map Guided Adaptive Activation Sparsification for Pix2pix Applications. - Wenyu Sun; Chen Tang; Zhuqing Yuan; Zhe Yuan; Huazhong Yang; Yongpan Liu (A-SSCC, 2020)

High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks. - Jingyu Wang 004; Songming Yu; Jinshan Yue; Zhe Yuan; Zhuqing Yuan; Huazhong Yang; Xueqing Li 002; Yongpan Liu (DAC, 2020)

High-Quality Single-Model Deep Video Compression with Frame-Conv3D and Multi-frame Differential Modulation. - Wenyu Sun; Chen Tang; Weigui Li; Zhuqing Yuan; Huazhong Yang; Yongpan Liu (ECCV (30), 2020)

Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems. - Keni Qiu; Mengying Zhao; Zhenge Jia; Jingtong Hu; Chun Jason Xue; Kaisheng Ma; Xueqing Li 002; Yongpan Liu; Vijaykrishnan Narayanan (ACM Great Lakes Symposium on VLSI, 2020)

RL Based Network Accelerator Compiler for Joint Compression Hyper-Parameter Search. - Xiaoyu Feng; Jinshan Yue; Zhe Yuan; Huazhong Yang; Yongpan Liu (ISCAS, 2020)

An Energy-Efficient Flexible Capacitive Pressure Sensing System. - Yuxuan Huang; Qinghang Zhao; Xiyuan Tang; Fang Su; Nan Sun 001; Huazhong Yang; Yongpan Liu (ISCAS, 2020)

FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface. - Mingyen Lee; Wenjun Tang; Bowen Xue; Juejian Wu; Mingyuan Ma; Yu Wang 002; Yongpan Liu; Deliang Fan; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (ISLPED, 2020)

Multi-channel precision-sparsity-adapted inter-frame differential data codec for video neural network processor. - Yixiong Yang; Zhe Yuan; Fang Su; Fanyang Cheng; Zhuqing Yuan; Huazhong Yang; Yongpan Liu (ISLPED, 2020)

14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec. - Zhe Yuan; Yixiong Yang; Jinshan Yue; Ruoyang Liu; Xiaoyu Feng; Zhiting Lin; Xiulong Wu; Xueqing Li 002; Huazhong Yang; Yongpan Liu (ISSCC, 2020)

14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse. - Jinshan Yue; Zhe Yuan; Xiaoyu Feng; Yifan He 003; Zhixiao Zhang; Xin Si; Ruhui Liu; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang; Yongpan Liu (ISSCC, 2020)

ADMP: An Adversarial Double Masks Based Pruning Framework For Unsupervised Cross-Domain Compression. - Xiaoyu Feng; Zhuqing Yuan; Guijin Wang; Yongpan Liu (CoRR, 2020)

High Area/Energy Efficiency RRAM CNN Accelerator with Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning. - Songming Yu; Yongpan Liu; Lu Zhang; Jingyu Wang 004; Jinshan Yue; Zhuqing Yuan; Xueqing Li 002; Huazhong Yang (CoRR, 2020)

Adaptive Structured Sparse Network for Efficient CNNs with Feature Regularization. - Chen Tang; Wenyu Sun; Zhuqing Yuan; Guijin Wang; Yongpan Liu (CoRR, 2020)

Low Overhead Online Data Flow Tracking for Intermittently Powered Non-Volatile FPGAs. - Xinyi Zhang 001; Clay Patterson; Yongpan Liu; Chengmo Yang; Chun Jason Xue; Jingtong Hu (ACM J. Emerg. Technol. Comput. Syst., 2020)

STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS. - Zhe Yuan; Yongpan Liu; Jinshan Yue; Yixiong Yang; Jingyu Wang 004; Xiaoyu Feng; Jian Zhao 004; Xueqing Li 002; Huazhong Yang (IEEE J. Solid State Circuits, 2020)

Investigation and Modeling of Multi-Node Body Channel Wireless Power Transfer. - Yuxuan Huang; Jian Zhao 004; Wenyu Sun; Huazhong Yang; Yongpan Liu (Sensors, 2020)

GAAS: An Efficient Group Associated Architecture and Scheduler Module for Sparse CNN Accelerators. - Jingyu Wang 004; Zhe Yuan; Ruoyang Liu; Xiaoyu Feng; Li Du; Huazhong Yang; Yongpan Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications. - Fei Tan; Yiming Wang; Yiming Yang; Liran Li; Tian Wang; Feng Zhang 014; Xinghua Wang; Jianfeng Gao 005; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

One-Shot Refresh: A Low-Power Low-Congestion Approach for Dynamic Memories. - Hongtao Zhong; Mingyang Gu; Yu Wang 002; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst., 2020)

Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules. - Yifan He 003; Jinshan Yue; Yongpan Liu; Huazhong Yang (ASP-DAC, 2021)

A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC. - Yuxuan Huang; Yifan He 003; Jinshan Yue; Huazhong Yang; Yongpan Liu (ASP-DAC, 2021)

A Sort-Less FPGA-Based Non-Maximum Suppression Accelerator using Multi-Thread Computing and Binary Max Engine for Object Detection. - Chaoming Fang; Habib Derbyshire; Wenyu Sun; Jinshan Yue; Haobing Shi; Yongpan Liu (A-SSCC, 2021)

PETRI: Reducing Bandwidth Requirement in Smart Surveillance by Edge-Cloud Collaborative Adaptive Frame Clustering and Pipelined Bidirectional Tracking. - Ruoyang Liu; Lu Zhang; Jingyu Wang 004; Huazhong Yang; Yongpan Liu (DAC, 2021)

Exploiting FeFET Switching Stochasticity for Low-Power Reconfigurable Physical Unclonable Function. - Xinrui Guo; Xiaoyang Ma; Franz Müller 001; Ricardo Olivo; Juejian Wu; Kai Ni 004; Thomas Kämpfe; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ESSDERC, 2021)

A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output. - He Zhang 011; Junzhan Liu; Kang Wang 001; Yunqian Fan; Shufeng Fu; Jinyu Bai; Biao Pan; Yongpan Liu; Weisheng Zhao (ICTA, 2021)

Almost-Nonvolatile IGZO-TFT-Based Near-Sensor In-Memory Computing. - Jialong Liu; Wenjun Tang; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ISCAS, 2021)

Challenges and Opportunities of Energy-Efficient CIM SoC Design for Edge AI Devices. - Jinshan Yue; Wenyu Sun; Huazhong Yang; Yongpan Liu (ISOCC, 2021)

Session 15 Overview: Compute-in-Memory Processors for Deep Neural Networks Machine Learning Subcommittee. - Jun Deguchi; Yongpan Liu; Yan Li (ISSCC, 2021)

F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors. - Sukhwan Lim; Yongpan Liu; Luca Benini; Tanay Karnik; Hsie-Chia Chang (ISSCC, 2021)

A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. - Jinshan Yue; Xiaoyu Feng; Yifan He 003; Yuxuan Huang; Yipeng Wang 009; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hung; et al. (ISSCC, 2021)

High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme. - Songming Yu; Lu Zhang; Jingyu Wang 004; Jinshan Yue; Zhuqing Yuan; Xueqing Li 002; Huazhong Yang; Yongpan Liu (NVMSA, 2021)

STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration. - Jinshan Yue; Yongpan Liu; Ruoyang Liu; Wenyu Sun; Zhe Yuan; Yung-Ning Tu; Yi-Ju Chen; Ao Ren; Yanzhi Wang; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang (IEEE J. Solid State Circuits, 2021)

Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control. - Linfang Wang; Wang Ye; Chunmeng Dou; Xin Si; Xiaoxin Xu; Jing Liu 035; Dashan Shang; Jianfeng Gao 005; Feng Zhang 014; Yongpan Liu; Meng-Fan Chang; Qi Liu 010 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Enabling Lower-Power Charge-Domain Nonvolatile In-Memory Computing With Ferroelectric FETs. - Guodong Yin; Yi Cai 003; Juejian Wu; Zhengyang Duan; Zhenhua Zhu; Yongpan Liu; Yu Wang 002; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

MaxTracker: Continuously Tracking the Maximum Computation Progress for Energy Harvesting ReRAM-based CNN Accelerators. - Keni Qiu; Nicholas Jao; Kunyu Zhou; Yongpan Liu; Jack Sampson; Mahmut Taylan Kandemir; Vijaykrishnan Narayanan (ACM Trans. Embed. Comput. Syst., 2021)

DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays. - Hongtao Zhong; Shengjie Cao; Li Jiang 002; Xia An; Vijaykrishnan Narayanan; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC. - Yuxuan Huang; Yifan He 003; Jinshan Yue; Wenyu Sun; Huazhong Yang; Yongpan Liu (ASP-DAC, 2022)

Dynamic CNN Accelerator Supporting Efficient Filter Generator with Kernel Enhancement and Online Channel Pruning. - Chen Tang; Wenyu Sun; Wenxun Wang; Yongpan Liu (ASP-DAC, 2022)

Toward Low-Bit Neural Network Training Accelerator by Dynamic Group Accumulation. - Yixiong Yang; Ruoyang Liu; Wenyu Sun; Jinshan Yue; Huazhong Yang; Yongpan Liu (ASP-DAC, 2022)

YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip. - Yiming Chen; Guodong Yin; Zhanhong Tan; Mingyen Lee; Zekun Yang; Yongpan Liu; Huazhong Yang; Kaisheng Ma; Xueqing Li 002 (DAC, 2022)

Hidden-ROM: A Compute-in-ROM Architecture to Deploy Large-Scale Neural Networks on Chip with Flexible and Scalable Post-Fabrication Task Transfer Capability. - Yiming Chen; Guodong Yin; Mingyen Lee; Wenjun Tang; Zekun Yang; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ICCAD, 2022)

C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations. - Yifan He 003; Yuxuan Huang; Jinshan Yue; Wenyu Sun; Lu Zhang; Yongpan Liu (ISCAS, 2022)

Efficient Neural Networks with Spatial Wise Sparsity Using Unified Importance Map. - Chen Tang; Wenyu Sun; Wenxun Wang; Zhuqing Yuan; Yongpan Liu (ISCAS, 2022)

Mixed-Precision Continual Learning Based on Computational Resistance Random Access Memory. - Yi Li 049; Woyu Zhang; Xiaoxin Xu; Yifan He 003; Danian Dong; Nanjia Jiang; Fei Wang; Zeyu Guo 002; Shaocong Wang; Chunmeng Dou; Yongpan Liu; Zhongrui Wang; et al. (Adv. Intell. Syst., 2022)

FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications. - Yiming Chen; Yushen Fu; Mingyen Lee; Sumitha George; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (CoRR, 2022)

ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key. - Jianfeng Wang; Zhonghao Chen; Jiahao Zhang; Yixin Xu 001; Tongguang Yu; Enze Ye; Ziheng Zheng; Huazhong Yang; Sumitha George; Yongpan Liu; Vijaykrishnan Narayanan; Xueqing Li 002 (CoRR, 2022)

GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph. - Yiming Chen; Guohao Dai; Mufeng Zhou; Mingyen Lee; Nagadastagiri Challapalle; Guodong Yin; Zekun Yang; Yongpan Liu; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (CoRR, 2022)

Ferroelectric FET-based strong physical unclonable function: a low-power, high-reliable and reconfigurable solution for Internet-of-Things security. - Xinrui Guo; Xiaoyang Ma; Franz Müller 001; Kai Ni 004; Thomas Kämpfe; Yongpan Liu; Vijaykrishnan Narayanan; Xueqing Li 002 (CoRR, 2022)

A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface. - Guodong Yin; Mufeng Zhou; Yiming Chen; Wenjun Tang; Zekun Yang; Mingyen Lee; Xirui Du; Jinshan Yue; Jiaxin Liu; Huazhong Yang; Yongpan Liu; Xueqing Li 002 (CoRR, 2022)

Guest Editorial: ACM JETC Special Issue on Hardware-Aware Learning for Medical Applications. - Yiyu Shi 001; Yongpan Liu; Jianxu Chen 001; Steve B. Jiang (ACM J. Emerg. Technol. Comput. Syst., 2022)

A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications. - Yixiong Yang; Yongpan Liu; Zhe Yuan; Wenyu Sun; Ruoyang Liu; Jingyu Wang 004; Jinshan Yue; Xiaoyu Feng; Zhuqing Yuan; Xueqing Li 002; Huazhong Yang (IEEE J. Solid State Circuits, 2022)

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse. - Jinshan Yue; Yongpan Liu; Zhe Yuan; Xiaoyu Feng; Yifan He 002; Wenyu Sun; Zhixiao Zhang; Xin Si; Ruhui Liu; Zi Wang; Meng-Fan Chang; Chunmeng Dou; et al. (IEEE J. Solid State Circuits, 2022)

PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs. - Jingyu Wang 004; Songming Yu; Zhuqing Yuan; Jinshan Yue; Zhe Yuan; Ruoyang Liu; Yanzhi Wang; Huazhong Yang; Xueqing Li 002; Yongpan Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems. - Yuxuan Huang; Yifan He 003; Jinshan Yue; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems. - Yuxuan Huang; Yifan He 003; Jingyu Wang 004; Jinshan Yue; Lu Zhang; Kaiwei Zou; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

StructADMM: Achieving Ultrahigh Efficiency in Structured Pruning for DNNs. - Tianyun Zhang; Shaokai Ye; Xiaoyu Feng; Xiaolong Ma; Kaiqi Zhang 003; Zhengang Li; Jian Tang 008; Sijia Liu 001; Xue Lin 001; Yongpan Liu; Makan Fardad; Yanzhi Wang (IEEE Trans. Neural Networks Learn. Syst., 2022)

CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications. - Xiaoyang Ma; Hongtao Zhong; Nuo Xiu; Yiming Chen; Guodong Yin; Vijaykrishnan Narayanan; Yongpan Liu; Kai Ni 004; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

SEFormer: Structure Embedding Transformer for 3D Object Detection. - Xiaoyu Feng; Heming Du; Hehe Fan; Yueqi Duan; Yongpan Liu (AAAI, 2023)

A Demonstration Platform for Large-Scaled Point Cloud Network Based on 28nm 2D/3D Unified Sparse Convolution Accelerator. - Xiaoyu Feng; Wenyu Sun; Shupei Fan; Chen Tang; Yixiong Yang; Jinshan Yue; Qingmin Liao; Huazhong Yang; Yongpan Liu (AICAS, 2023)

Semantic Guided Fine-Grained Point Cloud Quantization Framework for 3D Object Detection. - Xiaoyu Feng; Chen Tang; Zongkai Zhang; Wenyu Sun; Yongpan Liu (ASP-DAC, 2023)

Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity Analytics. - Ruoyang Liu; Chenhan Wei; Yixiong Yang; Wenxun Wang; Huazhong Yang; Yongpan Liu (ASP-DAC, 2023)

A 28nm 386.5GOPS/W Coarse-Grained DSP Using Configurable Processing Elements for Always-on Computation with FPGA Implementation. - Hedi Wang; Zengwei Wang; Yaolei Li; Chen Tang; Jinxu Gao; Huazhong Yang; Yongpan Liu (A-SSCC, 2023)

A 28nm 1.07TFLOPS/mm2 Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing. - Yixiong Yang; Ruoyang Liu; Chenhan Wei; Wenxun Wang; Wenyu Sun; Jinshan Yue; Huazhong Yang; Yongpan Liu (CICC, 2023)

Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM. - Mingyen Lee; Wenjun Tang; Yiming Chen; Juejian Wu; Hongtao Zhong; Yixin Xu 001; Yongpan Liu; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (DAC, 2023)

ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory. - Hongtao Zhong; Zhonghao Chen; Wenqin Huangfu; Chen Wang; Yixin Xu 001; Tianyi Wang; Yao Yu; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (DAC, 2023)

SOLE: Hardware-Software Co-design of Softmax and LayerNorm for Efficient Transformer Inference. - Wenxun Wang; Shuchang Zhou 001; Wenyu Sun; Peiqin Sun; Yongpan Liu (ICCAD, 2023)

Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices. - Juejian Wu; Tianyu Liao; Taixin Li; Yixin Xu 001; Vijaykrishnan Narayanan; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ICCAD, 2023)

Communication-aware Quantization for Deep Learning Inference Parallelization on Chiplet-based Accelerators. - Kaiwei Zou; Songyun Qu; Wen Li; Ying Wang 001; Huawei Li 001; Yongpan Liu (ICPADS, 2023)

A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture. - Zi Wang; Jinshan Yue; Chaojie He; Zhuoyu Dai; Feibin Xiang; Zhaori Cong; Yifan He 003; Xiaoyu Feng; Yongpan Liu (ISCAS, 2023)

A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. - Yifan He 003; Haikang Diao; Chen Tang; Wenbin Jia; Xiyuan Tang; Yuan Wang 001; Jinshan Yue; Xueqing Li 002; Huazhong Yang; Hongyang Jia; Yongpan Liu (ISSCC, 2023)

A 28nm 2D/3D Unified Sparse Convolution Accelerator with Block-Wise Neighbor Searcher for Large-Scaled Voxel-Based Point Cloud Network. - Wenyu Sun; Xiaoyu Feng; Chen Tang; Shupei Fan; Yixiong Yang; Jinshan Yue; Huazhong Yang; Yongpan Liu (ISSCC, 2023)

A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. - Jinshan Yue; Chaojie He; Zi Wang; Zhaori Cong; Yifan He 002; Mufeng Zhou; Wenyu Sun; Xueqing Li 002; Chunmeng Dou; Feng Zhang 014; Huazhong Yang; Yongpan Liu; et al. (ISSCC, 2023)

Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks. - Hongtao Zhong; Yu Zhu; Longfei Luo; Taixin Li; Chen Wang; Yixin Xu 001; Tianyi Wang; Yao Yu; Vijaykrishnan Narayanan; Yongpan Liu; Liang Shi 001; Huazhong Yang; et al. (ISVLSI, 2023)

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. - Jinshan Yue; Mingtao Zhan; Zi Wang; Yifan He 002; Yaolei Li; Songming Yu; Wenyu Sun; Lu Jie 001; Chunmeng Dou; Xueqing Li 002; Nan Sun 001; Huazhong Yang; et al. (VLSI Technology and Circuits, 2023)

CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration. - Yanan Sun 003; Dengfeng Wang; Liukai Xu; Yiming Chen; Zhi Li 058; Songyuan Liu; Weifeng He; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge. - Wenjun Tang; Mingyen Lee; Juejian Wu; Yixin Xu 001; Yao Yu; Yongpan Liu; Kai Ni 004; Yu Wang 002; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Reliable and Efficient Parallel Checkpointing Framework for Nonvolatile Processor With Concurrent Peripherals. - Tongda Wu; Kaisheng Ma; Jingtong Hu; Jason Xue 001; Jinyang Li 002; Xin Shi; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree. - Yifan He 003; Jinshan Yue; Xiaoyu Feng; Yuxuan Huang; Hongyang Jia; Jingyu Wang 004; Lu Zhang; Wenyu Sun; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution. - Yaolei Li; Jinshan Yue; Jingyu Wang 004; Chen Tang; Yifan He 003; Wenbin Jia; Kaiwei Zou; Lu Zhang; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array. - Lu Zhang; Dejun Mu; Yuxuan Huang; Jingyu Wang 004; Yifan He 003; Yaolei Li; Lizhou Liu; Kaiwei Zou; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations. - Yiming Chen; Yushen Fu; Mingyen Lee; Sumitha George; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An In-Memory-Computing Charge-Domain Ternary CNN Classifier. - Xiangxing Yang; Keren Zhu 001; Xiyuan Tang; Meizhi Wang; Mingtao Zhan; Nanshu Lu; Jaydeep P. Kulkarni; David Z. Pan; Yongpan Liu; Nan Sun 001 (IEEE J. Solid State Circuits, 2023)

SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree. - Yiming Chen; Guodong Yin; Mufeng Zhou; Wenjun Tang; Zekun Yang; Mingyen Lee; Xirui Du; Jinshan Yue; Jiaxin Liu; Huazhong Yang; Yongpan Liu; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Modularized Equalization Architecture With Transformer-Based Integrating Voltage Equalizer for the Series-Connected Battery Pack in Electric Bicycles. - Bin Xu; Lizhou Liu; Zhaotian Yan; Zhuqing Yuan; Lu Zhang; Wei Zhou 024; Ruikun Mai; Zhengyou He; Yongpan Liu; Huazhong Yang (IEEE Trans. Ind. Electron., 2023)

A Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference. - Songming Yu; Yifan He 003; Hongyang Jia; Wenyu Sun; Mufeng Zhou; Luchang Lei; Wentao Zhao; Guofu Ma; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Low-Power and Scalable BEOL-Compatible IGZO TFT eDRAM-Based Charge-Domain Computing. - Wenjun Tang; Jialong Liu; Chen Sun 010; Zijie Zheng; Yongpan Liu; Huazhong Yang; Chen Jiang; Kai Ni 004; Xiao Gong; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 28nm 166.9 TOPS/W x Mb/mm2 DRAM-Free QLC Compute-in-ROM Macro Supporting High Task-Level Inference Energy Efficiency for Tiny AI Edge Devices. - Ling-An Cheong; Chen Wang; Mufeng Zhou; Tianyu Liao; Mingyen Lee; Yue Ke; Wenjun Tang; Yiming Chen; Xirui Du; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (A-SSCC, 2024)

A Unified Microrobotic Visual-Perception Processor with 62.2-FPS/mm2 and 103-uJ/frame Navigation in 28nm. - Shuyuan Zhang; Yujin Wang; Yifan He 003; Yuchen Su; Huazhong Yang; Yongpan Liu; Hongyang Jia (A-SSCC, 2024)

A 28nm 1.2GHz 5.27TOPS/W Scalable Vision/Point Cloud Deep Fusion Processor with CAM-based Universal Mapping Unit for BEVFusion Applications. - Xiaoyu Feng; Wenyu Sun; Xinyuan Lin; Shupei Fan; Huazhong Yang; Yongpan Liu (CICC, 2024)

A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM. - Guodong Yin; Yiming Chen; Mingyen Lee; Xirui Du; Yue Ke; Wenjun Tang; Zhonghao Chen; Mufeng Zhou; Jinshan Yue; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (CICC, 2024)

A 1024-Channel Neurostimulation System Enabled by Photolithographic Organic Thin-Film Transistors with High Uniformity. - Bowen Liu; Yangkun Hou; Yueshan Qin; Jiwei Zou; Hanbin Ma; Yongpan Liu; Huazhong Yang; Xueqing Li 002; Chen Jiang (ISCAS, 2024)

34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing. - Yifan He 003; Shupei Fan; Xuan Li; Luchang Lei; Wenbin Jia; Chen Tang; Yaolei Li; Zongle Huang; Zhike Du; Jinshan Yue; Xueqing Li 002; Huazhong Yang; et al. (ISSCC, 2024)

Exploring Approximation and Dataflow Co-Optimization for Scalable Transformer Inference Architecture on the Edge. - Liu He; Yujin Wang; Zongle Huang; Shupei Fan; Chen Tang; Shuyuan Zhang; Luchang Lei; Huazhong Yang; Yongpan Liu; Hongyang Jia (SOCC, 2024)

A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications. - Zhuoyu Dai; Shengzhe Yan; Zhaori Cong; Zeyu Guo 002; Yifan He 002; Wenyu Sun; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Yongpan Liu; Ming Liu 022 (VLSI Technology and Circuits, 2024)

A 28nm 4.35TOPS/mm2 Transformer Accelerator with Basis-vector Based Ultra Storage Compression, Decomposed Computation and Unified LUT-Assisted Cores. - Chen Tang; Xinyuan Lin; Zongle Huang; Wenyu Sun; Hongyang Jia; Yongpan Liu (VLSI Technology and Circuits, 2024)

Hecaton: Training and Finetuning Large Language Models with Scalable Chiplet Systems. - Zongle Huang; Shupei Fan; Chen Tang; Xinyuan Lin; Shuwen Deng; Yongpan Liu (CoRR, 2024)

GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility. - Yiming Chen; Mingyen Lee; Guohao Dai; Mufeng Zhou; Nagadastagiri Challapalle; Tianyi Wang; Yao Yu; Yongpan Liu; Yu Wang 002; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (IEEE Trans. Emerg. Top. Comput., 2024)

TFT-Based Near-Sensor In-Memory Computing: Circuits and Architecture Perspectives of Large-Area eDRAM and ROM CiM Chips. - Jialong Liu; Wenjun Tang; Hongtian Li; Deyun Chen; Weihang Long; Yongpan Liu; Chen Jiang; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design. - Chaojie He; Zi Wang; Feibin Xiang; Zhuoyu Dai; Yifan He 003; Jinshan Yue; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

ULSeq-TA: Ultra-Long Sequence Attention Fusion Transformer Accelerator Supporting Grouped Sparse Softmax and Dual-Path Sparse LayerNorm. - Jingyu Wang 004; Lu Zhang; Xueqing Li 002; Huazhong Yang; Yongpan Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Module-Level Configuration Methodology for Programmable Camouflaged Logic. - Jianfeng Wang; Zhonghao Chen; Jiahao Zhang; Yixin Xu 001; Tongguang Yu; Ziheng Zheng; Enze Ye; Sumitha George; Huazhong Yang; Yongpan Liu; Kai Ni 004; Vijaykrishnan Narayanan; et al. (ACM Trans. Design Autom. Electr. Syst., 2024)

Weight and Multiply-Accumulation Sparsity-Aware Non-Volatile Computing-in-Memory System. - Yuxuan Huang; Yongpan Liu; Lifu Cheng; Kuntuo Zhu; Kui Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. - Jinshan Yue; Yongpan Liu; Xiaoyu Feng; Yifan He 002; Jingyu Wang 004; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hong; et al. (IEEE J. Solid State Circuits, 2024)

Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm2 Density in 65-nm CMOS. - Guodong Yin; Yiming Chen; Mufeng Zhou; Wenjun Tang; Mingyen Lee; Zekun Yang; Tianyu Liao; Xirui Du; Vijaykrishnan Narayanan; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (IEEE J. Solid State Circuits, 2024)

A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture. - Shengzhe Yan; Jinshan Yue; Chaojie He; Zi Wang; Zhaori Cong; Yifan He 002; Mufeng Zhou; Wenyu Sun; Xueqing Li 002; Chunmeng Dou; Feng Zhang 014; Huazhong Yang; et al. (IEEE J. Solid State Circuits, 2024)

A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching. - Xiaoyu Feng; Wenyu Sun; Chen Tang; Xinyuan Lin; Jinshan Yue; Huazhong Yang; Yongpan Liu (IEEE J. Solid State Circuits, 2024)

A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis. - Ruoyang Liu; Chenhan Wei; Yixiong Yang; Wenxun Wang; Binbin Yuan; Huazhong Yang; Yongpan Liu (IEEE J. Solid State Circuits, 2024)

RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel. - Lu Zhang; Dejun Mu; Jingyu Wang 004; Ruoyang Liu; Yifan He 003; Yaolei Li; Yu Tai; Shengbing Zhang; Xiaoya Fan; Huazhong Yang; Yongpan Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Heterogeneous Microprocessor for Intermittent AI Inference Using Nonvolatile-SRAM-Based Compute-In-Memory. - Tongda Wu; Luchang Lei; Yifan He 003; Wenbin Jia; Songming Yu; Yuxuan Huang; Hongyang Jia; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices. - Zhuoyu Dai; Feibin Xiang; Xiangqu Fu; Yifan He 003; Wenyu Sun; Yongpan Liu; Guanhua Yang; Feng Zhang 014; Jinshan Yue; Ling Li 013 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Fully Quantized Training Accelerator for Diffusion Network With Tensor Type & Noise Strength Aware Precision Scheduling. - Ruoyang Liu; Wenxun Wang; Chen Tang; Weichen Gao; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

3D-METRO: Deploy Large-Scale Transformer Model on A Chip Using Transistor-Less 3D-Metal-ROM-Based Compute-in-Memory Macro. - Yiming Chen; Xirui Du; Guodong Yin; Wenjun Tang; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ASP-DAC, 2025)

MPICC: Multiple-Precision Inter-Combined MAC Unit with Stochastic Rounding for Ultra-Low-Precision Training. - Leran Huang; Yongpan Liu; Xinyuan Lin; Chenhan Wei; Wenyu Sun; Zengwei Wang; Boran Cao; Chi Zhang; Xiaoxia Fu; Wentao Zhao; Sheng Zhang (ASP-DAC, 2025)

DCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task Level. - Tianyi Yu; Tianyu Liao; Mufeng Zhou; Xiaotian Chu; Guodong Yin; Mingyen Lee; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ASP-DAC, 2025)

Deploying Diffusion Models with Scheduling Space Search and Memory Overflow Prevention Based on Graph Optimization. - Hao Zhou 008; Yang Liu 376; Hongji Wang; Enhao Tang; Shun Li; Yifan Zhang; Guohao Dai; Yongpan Liu; Kun Wang 005 (ASP-DAC, 2025)

Pro-Cache-CIM: A 28nm 69.4TOPS/W Product-Cache-based Digital-Compute-in-Memory Macro Leveraging Data Locality Pattern in Vision AI Tasks. - Wenbin Jia; Yifan He 003; Xiang Li; Yixuan Xie; Zongle Huang; Wenxun Wang; Boju Chen; Yaolei Li; Jinshan Yue; Xueqing Li 002; Huazhong Yang; Hongyang Jia; et al. (CICC, 2025)

A 28nm 3.14 TFLOP/W BF16 LLM Fine-Tuning Processor with Asymmetric Quantization Computing for AI PC. - Xinyuan Lin; Leran Huang; Chenhan Wei; Wenbin Jia; Hedi Wang; Wenxun Wang; Hongyang Jia; Huazhong Yang; Yongpan Liu (CICC, 2025)

CCE: A 28nm Content Creation Engine with Asymmetric Computing, Semantic-Driven Instruction Generation and Collision-Free Outlier Mapper for Video Generation. - Chen Tang; Zongle Huang; Wenxun Wang; Yifan He; Shupei Fan; Xiaoyu Feng; Wenyu Sun; Yongpan Liu (CICC, 2025)

DSC-ROM: A Fully Digital Sparsity-Compressed Compute-in-ROM Architecture for on-Chip Deployment of Large-Scale DNNs. - Tianyi Yu; Zhonghao Chen; Yiming Chen; Shuang Wang; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (DATE, 2025)

ADDR: Architecture Design and Model Deployment Optimization for Hybrid SRAM-ROM Compute-in-Memory. - Teng Wan; Yiming Chen; Zekai Chen; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ACM Great Lakes Symposium on VLSI, 2025)

An Integer-only Quantization Framework for Edge Deployment of Large Language Models. - Yaqi Hu; Zhuqing Yuan; Weichen Gao; Sheng Zhang; Yongpan Liu (ISCAS, 2025)

A Threshold-Voltage Compensation Circuit for Organic Thin-Film Transistor Active-Matrix Neurostimulation System. - Shikai Wang; Bowen Liu; Xueqing Li 002; Huazhong Yang; Yongpan Liu; Chen Jiang (ISCAS, 2025)

1.78mJ/Frame 373fps 3D GS Processor Based on Shape-Aware Hybrid Architecture Using Earlier Computation Skipping and Gaussian Cache Scheduler. - Xiaoyu Feng; Hedi Wang; Chen Tang; Tongda Wu; Huazhong Yang; Yongpan Liu (ISSCC, 2025)

A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference. - Haikang Diao; Yifan He 003; Xuan Li; Chen Tang; Wenbin Jia; Jinshan Yue; Haoyang Luo; Jiahao Song; Xueqing Li 002; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (IEEE J. Solid State Circuits, 2025)

Enhancing Memory Efficiency in Large Language Model Training Through Chronos-aware Pipeline Parallelism. - Xinyuan Lin; Chenlu Li; Zongle Huang; Chunyu Wang; Bo Xiao; Huazhong Yang; Shishi Duan; Yongpan Liu (CoRR, 2025)

A Scalable BEV Perception Processor for Image/Point Cloud Fusion Applications Using CAM-Based Universal Mapping Unit. - Xiaoyu Feng; Xinyuan Lin; Huazhong Yang; Yongpan Liu; Wenyu Sun (IEEE J. Solid State Circuits, 2025)

Improving Transformer Inference Through Optimized Nonlinear Operations With Quantization-Approximation-Based Strategy. - Wenxun Wang; Wenyu Sun; Yongpan Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

MoESD: Unveil Speculative Decoding's Potential for Accelerating Sparse MoE. - Zongle Huang; Lei Zhu; Zongyuan Zhan; Ting Hu; Weikai Mao; Xianzhi Yu; Yongpan Liu; Tianyu Zhang (CoRR, 2025)

Enabling Energy-Efficient Homomorphic Encryption Evaluation via eDRAM-Based In-Situ Computing in an Edge Processor. - Luchang Lei; Yongqing Zhu; Xinhang Zou; Zhou Zhang 016; Zian Zhao; Yifan He 003; Gangfeng Du; Zhenyu Guan; Huazhong Yang; Yongpan Liu; Song Bian 001; Hongyang Jia (IEEE J. Solid State Circuits, 2025)

An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet. - Zhihang Qian; Shengzhe Yan; Zhuoyu Dai; Zeyu Guo 002; Zhaori Cong; Yifan He 002; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Yongpan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2025)