24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs. - Chih-Wei Yao; Wing Fai Loke; Ronghua Ni; Yongping Han; Haoyang Li; Kunal Godbole; Yongrong Zuo; Sangsoo Ko; Nam-Seog Kim 001; Sangwook Han; Ikkyun Jo; Joonhee Lee; et al. (ISSCC, 2017)

A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction. - Wanghua Wu; Chih-Wei Yao; Kunal Godbole; Ronghua Ni; Pei-Yuan Chiang; Yongping Han; Yongrong Zuo; Ashutosh Verma; Ivan Siu-Chuang Lu; Sang Won Son; Thomas Byunghak Cho (IEEE J. Solid State Circuits, 2019)