A 10-bit Two-Stage Pipeline SAR ADC in 55nm CMOS for Compute-in-Memory Applications. - Xiapeng Xu; Yongteng Ma; Xuliang Yu; Fanzi Meng; Wei-Han Yu; Liang Zhao (APCCAS, 2024)

An SRAM Compute-In-Memory Macro Based on Direct Coupling SAR ADC and DAC Reuse. - Yongteng Ma; Xuliang Yu; Zhichao Tan; Liang Zhao (ISCAS, 2024)