Precise Localization of an Autonomous Car Based on Probabilistic Noise Models of Road Surface Marker Features Using Multiple Cameras. - Kichun Jo; Yongwoo Jo; Jae Kyu Suhr; Ho Gi Jung; Myoungho Sunwoo (IEEE Trans. Intell. Transp. Syst., 2015)

An autonomous lane-level road map building using low-cost sensors. - Yongwoo Jo; Seung-Jun Han; Dongjin Lee; Kyoungwook Min; Jeongdan Choi (ICMV, 2018)

Vehicle re-identification for a parking lot toll system using convolutional neural networks. - Dongjin Lee; Yongwoo Jo; Seung-Jun Han; Jungyu Kang; Kyoungwook Min; Jeongdan Choi; Cheong Hee Park (ICMV, 2018)

Robust Ego-motion Estimation and Map Matching Technique for Autonomous Vehicle Localization with High Definition Digital Map. - Seung-Jun Han; Jungyu Kang; Yongwoo Jo; Dongjin Lee; JeongDan Choi (ICTC, 2018)

153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier. - Seojin Choi; Seyeon Yoo; Yongsun Lee; Yongwoo Jo; Jeonghyun Lee; Younghyun Lim; Jaehyouk Choi (VLSI Circuits, 2018)

An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique. - Younghyun Lim; Jeonghyun Lee; Suneui Park; Yongwoo Jo; Jaehyouk Choi (IEEE J. Solid State Circuits, 2018)

Real-time road surface marking detection from a bird's-eye view image using convolutional neural networks. - Jungyu Kang; Yongwoo Jo; Dongjin Lee; Seung-Jun Han; Kyoungwook Min; Jeongdan Choi (ICMV, 2019)

An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114. - Seojin Choi; Seyeon Yoo; Yongsun Lee; Yongwoo Jo; Jeonghyun Lee; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2019)

17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator. - Younghyun Lim; Juyeop Kim; Yongwoo Jo; Jooeun Bang; Seyeon Yoo; Hangi Park; Heein Yoon; Jaehyouk Choi (ISSCC, 2020)

32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique. - Juyeop Kim; Yongwoo Jo; Younghyun Lim; Taeho Seong; Hangi Park; Seyeon Yoo; Yongsun Lee; Seojin Choi; Jaehyouk Choi (ISSCC, 2021)

A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop. - Younghyun Lim; Juyeop Kim; Yongwoo Jo; Jooeun Bang; Jaehyouk Choi (IEEE J. Solid State Circuits, 2022)

A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier. - Yongwoo Jo; Juyeop Kim; Yuhwan Shin; Chanwoong Hwang; Hangi Park; Jaehyouk Choi (ISSCC, 2023)

A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces. - Yuhwan Shin; Yongwoo Jo; Juyeop Kim; Junseok Lee; Jongwha Kim; Jaehyouk Choi (ISSCC, 2023)

A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier. - Yongwoo Jo; Juyeop Kim; Yuhwan Shin; Hangi Park; Chanwoong Hwang; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2023)

Field Experiments and Validation of Cooperative Driving for Conneced Automated Vehicle. - Yoo-seung Song; Shin Kyung Lee; Yongwoo Jo; Jooyoung Kim; Kyoung-Wook Min (ICTC, 2024)

10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique. - Yuhwan Shin; Junseok Lee; Juyeop Kim; Yongwoo Jo; Jaehyouk Choi (ISSCC, 2024)

A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation. - Juyeop Kim; Yongwoo Jo; Hangi Park; Taeho Seong; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2024)

A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces. - Yuhwan Shin; Yongwoo Jo; Juyeop Kim; Junseok Lee; Jongwha Kim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2025)