Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. - Yonsang Cho; Irith Pomeranz; Sudhakar M. Reddy (ISQED, 2004)

On reducing test application time for scan circuits using limited scan operations and transfer sequences. - Yonsang Cho; Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Multi-die Parallel Test Fabric for Scalability and Pattern Reusability. - Arani Sinha; Yonsang Cho; Jon Easter; Meizel V. Leiva Rojas (ITC, 2022)