Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Gil-Hoon Cha; Jin-Hyeok Baek; Daesik Moon; Yoon-Joo Eom; Tae-Sung Kim; Hyunyoon Cho; Young Hoon Son; Seonghwan Kim 002; et al. (A-SSCC, 2017)

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme. - Chang-Kyo Lee; Yoon-Joo Eom; Jin-Hee Park; Junha Lee; Hye-Ran Kim; Kihan Kim; Young Choi; Ho-Jun Chang; Jonghyuk Kim; Jong-Min Bang; Seungjun Shin; Hanna Park; et al. (ISSCC, 2017)