Novel bootstrapped CMOS differential logic family for ultra-low voltage SoCs. - Byung Hwa Jung; Sung-Chan Kang; Jae-Hyuk Oh; Yoon-Suk Park; Yong-Ki Kim 002; Yonggu Kang; Jong-Woo Kim; Bai-Sun Kong (IEICE Electron. Express, 2008)

New low-voltage small-area mixed-voltage I/O buffer. - Joung-Yeal Kim; Yoon-Suk Park; Young-Hyun Jun; Bai-Sun Kong (IEICE Electron. Express, 2009)

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation. - Young-Won Kim; Joo-Seong Kim; Jae-Hyuk Oh; Yoon-Suk Park; Jong-Woo Kim; Kwang-Il Park; Bai-Sun Kong; Young-Hyun Jun (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. - Ki Chul Chun; Yonggyu Chu; Jin-Seok Heo; Tae-Sung Kim; Soohwan Kim; Hui-Kap Yang; Mi-Jo Kim; Chang-Kyo Lee; Ju-Hwan Kim; Hyunchul Yoon; Chang-Ho Shin; Sang-uhn Cha; et al. (ISSCC, 2018)