S-COI : The Secure Conflicts of Interest Model for Multilevel Secure Database Systems. - Chanjung Park; Seog Park; Yoongu Kim (DASFAA, 2004)

ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. - Yoongu Kim; Dongsu Han; Onur Mutlu; Mor Harchol-Balter (HPCA, 2010)

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. - Yoongu Kim; Michael Papamichael; Onur Mutlu; Mor Harchol-Balter (MICRO, 2010)

Thread Cluster Memory Scheduling. - Yoongu Kim; Michael Papamichael; Onur Mutlu; Mor Harchol-Balter (IEEE Micro, 2011)

A case for exploiting subarray-level parallelism (SALP) in DRAM. - Yoongu Kim; Vivek Seshadri; Donghyuk Lee; Jamie Liu; Onur Mutlu (ISCA, 2012)

Tiered-latency DRAM: A low latency and low cost DRAM architecture. - Donghyuk Lee; Yoongu Kim; Vivek Seshadri; Jamie Liu; Lavanya Subramanian; Onur Mutlu (HPCA, 2013)

MISE: Providing performance predictability and improving fairness in shared main memory systems. - Lavanya Subramanian; Vivek Seshadri; Yoongu Kim; Ben Jaiyen; Onur Mutlu (HPCA, 2013)

An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms. - Jamie Liu; Ben Jaiyen; Yoongu Kim; Chris Wilkerson; Onur Mutlu (ISCA, 2013)

Linearly compressed pages: a low-complexity, low-latency main memory compression framework. - Gennady Pekhimenko; Vivek Seshadri; Yoongu Kim; Hongyi Xin; Onur Mutlu; Phillip B. Gibbons; Michael A. Kozuch; Todd C. Mowry (MICRO, 2013)

RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization. - Vivek Seshadri; Yoongu Kim; Chris Fallin; Donghyuk Lee; Rachata Ausavarungnirun; Gennady Pekhimenko; Yixin Luo; Onur Mutlu; Phillip B. Gibbons; Michael A. Kozuch; Todd C. Mowry (MICRO, 2013)

Memory Systems. - Yoongu Kim; Onur Mutlu (Computing Handbook, 3rd ed. (1), 2014)

Improving DRAM performance by parallelizing refreshes with accesses. - Kevin Kai-Wei Chang; Donghyuk Lee; Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Yoongu Kim; Onur Mutlu (HPCA, 2014)

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. - Yoongu Kim; Ross Daly; Jeremie S. Kim; Chris Fallin; Ji-Hye Lee; Donghyuk Lee; Chris Wilkerson; Konrad Lai; Onur Mutlu (ISCA, 2014)

The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study. - Samira Manabi Khan; Donghyuk Lee; Yoongu Kim; Alaa R. Alameldeen; Chris Wilkerson; Onur Mutlu (SIGMETRICS, 2014)

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case. - Donghyuk Lee; Yoongu Kim; Gennady Pekhimenko; Samira Manabi Khan; Vivek Seshadri; Kevin Kai-Wei Chang; Onur Mutlu (HPCA, 2015)

Ramulator: A Fast and Extensible DRAM Simulator. - Yoongu Kim; Weikun Yang; Onur Mutlu (IEEE Comput. Archit. Lett., 2016)

Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses. - Kevin Kai-Wei Chang; Donghyuk Lee; Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Yoongu Kim; Onur Mutlu (CoRR, 2016)

RowHammer: Reliability Analysis and Security Implications. - Yoongu Kim; Ross Daly; Jeremie S. Kim; Chris Fallin; Ji-Hye Lee; Donghyuk Lee; Chris Wilkerson; Konrad Lai; Onur Mutlu (CoRR, 2016)

Adaptive-Latency DRAM (AL-DRAM). - Donghyuk Lee; Yoongu Kim; Gennady Pekhimenko; Samira Manabi Khan; Vivek Seshadri; Kevin Kai-Wei Chang; Onur Mutlu (CoRR, 2016)

Tiered-Latency DRAM (TL-DRAM). - Donghyuk Lee; Yoongu Kim; Vivek Seshadri; Jamie Liu; Lavanya Subramanian; Onur Mutlu (CoRR, 2016)

Improving DRAM Performance by Parallelizing Refreshes with Accesses. - Kevin K. Chang; Donghyuk Lee; Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Yoongu Kim; Onur Mutlu (CoRR, 2017)

Reducing DRAM Refresh Overheads with Refresh-Access Parallelism. - Kevin K. Chang; Donghyuk Lee; Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Yoongu Kim; Onur Mutlu (CoRR, 2018)

Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism. - Yoongu Kim; Vivek Seshadri; Donghyuk Lee; Jamie Liu; Onur Mutlu (CoRR, 2018)

Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins. - Donghyuk Lee; Yoongu Kim; Gennady Pekhimenko; Samira Manabi Khan; Vivek Seshadri; Kevin K. Chang; Onur Mutlu (CoRR, 2018)

Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost. - Donghyuk Lee; Yoongu Kim; Vivek Seshadri; Jamie Liu; Lavanya Subramanian; Onur Mutlu (CoRR, 2018)

RowClone: Accelerating Data Movement and Initialization Using DRAM. - Vivek Seshadri; Yoongu Kim; Chris Fallin; Donghyuk Lee; Rachata Ausavarungnirun; Gennady Pekhimenko; Yixin Luo; Onur Mutlu; Phillip B. Gibbons; Michael A. Kozuch; Todd C. Mowry (CoRR, 2018)

Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems. - Lavanya Subramanian; Vivek Seshadri; Yoongu Kim; Ben Jaiyen; Onur Mutlu (CoRR, 2018)

Half-Double: Hammering From the Next Row Over. - Andreas Kogler; Jonas Juffinger; Salman Qazi; Yoongu Kim; Moritz Lipp; Nicolas Boichat; Eric Shiu; Mattias Nissler; Daniel Gruss (USENIX Security Symposium, 2022)