Extracting Events from Web Documents for Social Media Monitoring Using Structured SVM. - Yoonjae Choi; Pum-Mo Ryu; Hyunki Kim; Changki Lee (IEICE Trans. Inf. Syst., 2013)

29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. - Yeonho Lee 002; Yoonjae Choi; Sang-Geun Bae; Jaehun Jun; Junyoung Song; Sewook Hwang; Chulwoo Kim (ISSCC, 2017)

12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. - Yeonho Lee 002; Yoonjae Choi; Chulwoo Kim (ASP-DAC, 2018)

A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX. - Jeongsik Yoo; Yeonho Lee 002; Yoonjae Choi; Hyunsu Park; Sanghune Park; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. - Yeonho Lee 002; Yoonjae Choi; Junyoung Song; Sewook Hwang; Sang-Geun Bae; Jaehun Jun; Chulwoo Kim (IEEE J. Solid State Circuits, 2019)

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector. - Yoonjae Choi; Sewook Hwang; Yeonho Lee 002; Hyunsu Park; Jonghyuck Choi; Jincheol Sim; Chulwoo Kim (IEEE Access, 2021)

A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. - Hyunsu Park; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Gyutae Park; Jinil Chung; Kyeong-Min Kim; Hae-Kang Jung; Hyungsoo Kim; Junhyun Chun; et al. (IEEE J. Solid State Circuits, 2021)

30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links. - Hyunsu Park; Junyoung Song; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Jeongsik Yoo; Chulwoo Kim (IEEE J. Solid State Circuits, 2021)

A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS. - Yoonjae Choi; Yeonho Lee 002; Hyunsu Park; Jonghyuck Choi; Jincheol Sim; Youngwook Kwon; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 266-3750 MHz Wide-Range Adaptive Phase-Rotator-Based All Digital DLL for LPDDR5 Controllers. - Jeewan Lee; Yoonjae Choi; Chulwoo Kim (ISCAS, 2022)

A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces. - Hyunsu Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Youngwook Kwon; Junyoung Song; Chulwoo Kim (ISSCC, 2022)

A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations. - Hyunsu Park; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Chulwoo Kim (IEEE J. Solid State Circuits, 2022)

Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme. - Jonghyuck Choi; Yoonjae Choi; Hyunsu Park; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces. - Youngwook Kwon; Hyunsu Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Seungwoo Park; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 2.4-8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input-Output Phase Detection. - Hyunsu Park; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End. - Jincheol Sim; Yeonho Lee 002; Hyunsu Park; Yoonjae Choi; Jonghyuck Choi; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications. - Seungwoo Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Hyunsu Park; Youngwook Kwon; Chulwoo Kim (ISSCC, 2023)

A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces. - Yoonjae Choi; Hyunsu Park; Jonghyuck Choi; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Chulwoo Kim (IEEE J. Solid State Circuits, 2023)

A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces. - Youngwook Kwon; Hyunsu Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Seungwoo Park; Kyeong-Min Kim; Changkyu Choi; Hae-Kang Jung; Chulwoo Kim (IEEE J. Solid State Circuits, 2023)

A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces. - Seongcheol Kim; Jincheol Sim; Hyunsu Park; Yoonjae Choi; Jonghyuck Choi; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE. - Jonghyuck Choi; Yoonjae Choi; Hyunsu Park; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance. - Jincheol Sim; Hyunsu Park; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector. - Yoonjae Choi; Hyunsu Park; Jonghyuck Choi; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Changmin Sim; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 4-nm 9.6-Gb/s/pin LPDDR5X PHY With Adaptive Driver Strength Control and Fast Periodic Training for Full DVFS DRAM. - Yoonjae Choi; Jaegeun Song; Daero Kim; Myunggon Kim; Jiyeon Park; Jinho Choi; Changki Kwon; Minho Seo; Jihun Oh; Shinyoung Yi 002; Billy Koo; Kwanyeob Chae; et al. (A-SSCC, 2024)

A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection. - Kwanyeob Chae; Jaegeun Song; Yoonjae Choi; Jiyeon Park; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Kyeongkeun Kang; Eunsu Kim; Juyoung Kim; et al. (IEEE J. Solid State Circuits, 2024)

A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces. - Jonghyuck Choi; Yoonjae Choi; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances. - Jincheol Sim; Changmin Sim; Hyunsu Park; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Jong-Min Kim; Ju-Hyung Lee 001; Young-Chai Ko; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces. - Hyoshin Kang; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling. - Seungwoo Park; Yoonjae Choi; Jonghyuck Choi; Jincheol Sim; Youngwook Kwon; Changmin Sim; Seongcheol Kim; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces. - Seongcheol Kim; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Changmin Sim; Junseob So; Taehyeong Park; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces. - Yoonjae Choi; Changmin Sim; Jonghyuck Choi; Jincheol Sim; Hyunsu Park; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 28-Gb/s Single-Ended PAM-4 Transceiver With Active-Inductor Equalizer and Amplitude- Detection LSB Decoder for Memory Interfaces. - Hwaseok Shin; Hyoshin Kang; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Junseob So; Taehwan Kim; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 52-Gb/s Low-Power PAM-4 Baud-Rate CDR Using Pattern-Based Phase Detector for Short-Reach Applications. - Seungwoo Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Hyunsu Park; Youngwook Kwon; Changmin Sim; Seongcheol Kim; Chulwoo Kim (IEEE J. Solid State Circuits, 2025)