A "divide and conquer" technique for the design of wide dynamic range continuous time filters. - George Palaskas; Yannis P. Tsividis (ISCAS (1), 2001)

"Noninvasive" techniques for syllabic companding in signal processors. - László Tóth 007; George Palaskas; Yannis P. Tsividis (ISCAS (1), 2001)

Design considerations and experimental evaluation of a syllabic companding audio frequency filter. - George Palaskas; Yannis P. Tsividis (ISCAS (3), 2002)

A power efficient channel selection filter/coarse AGC with no range switching transients. - Yorgos Palaskas; Yannis P. Tsividis; Vito Boccuzzi (CICC, 2003)

Power-area-DR-frequency-selectivity tradeoffs in weakly nonlinear active filters. - Yorgos Palaskas; Yannis P. Tsividis (ISCAS (1), 2003)

Dynamic range optimization of weakly nonlinear, fully balanced, Gm-C filters with power dissipation constraints. - Yorgos Palaskas; Yannis P. Tsividis (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A "divide and conquer" technique for implementing wide dynamic range continuous-time filters. - Yorgos Palaskas; Yannis P. Tsividis; Vladimir I. Prodanov; Vito Boccuzzi (IEEE J. Solid State Circuits, 2004)

A 90-nm MOS-only 3-11GHz transmitter for UWB. - Yorgos Palaskas; Ralph E. Bishop; Ashoke Ravi; Krishnamurthy Soumyanath (CICC, 2005)

A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction. - Yorgos Palaskas; Stewart S. Taylor; Stefano Pellerano; Ian A. Rippke; Ralph E. Bishop; Ashoke Ravi; Hasnain Lakdawala; Krishnamurthy Soumyanath (CICC, 2005)

A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS. - Sunghyun Park 006; Yorgos Palaskas; Ashoke Ravi; Ralph E. Bishop; Michael P. Flynn (CICC, 2006)

A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS. - Yorgos Palaskas; Ashoke Ravi; Stefano Pellerano; Brent R. Carlton; Mostafa A. Elmala; Ralph E. Bishop; Gaurab Banerjee; Rich B. Nicholls; Stanley K. Ling; Stewart S. Taylor; Krishnamurthy Soumyanath (ISSCC, 2006)

A 4GS/s 4b Flash ADC in 0.18µm CMOS. - Sunghyun Park 006; Yorgos Palaskas; Michael P. Flynn (ISSCC, 2006)

A 5-GHz 108-Mb/s 2 $ times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${ rm P}_{ rm 1dB}$ Power Amplifiers in 90-nm CMOS. - Yorgos Palaskas; Ashoke Ravi; Stefano Pellerano; Brent R. Carlton; Mostafa A. Elmala; Ralph E. Bishop; Gaurab Banerjee; Rich B. Nicholls; Stanley K. Ling; Nati Dinur; Stewart S. Taylor; Krishnamurthy Soumyanath (IEEE J. Solid State Circuits, 2006)

A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process. - Yorgos Palaskas; Stewart S. Taylor; Stefano Pellerano; Ian A. Rippke; Ralph E. Bishop; Ashoke Ravi; Hasnain Lakdawala; Krishnamurthy Soumyanath (IEEE J. Solid State Circuits, 2006)

A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS. - Stefano Pellerano; Yorgos Palaskas; Krishnamurthy Soumyanath (ESSCIRC, 2007)

A 4-GS/s 4-bit Flash ADC in 0.18-µm CMOS. - Sunghyun Park 006; Yorgos Palaskas; Michael P. Flynn (IEEE J. Solid State Circuits, 2007)

MIMO techniques for high data rate radio communications. - Yorgos Palaskas; Ashoke Ravi; Stefano Pellerano (CICC, 2008)

A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS. - Stefano Pellerano; Rajarshi Mukhopadhyay; Ashoke Ravi; Joy Laskar; Yorgos Palaskas (ISSCC, 2008)

A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation. - Jeffrey S. Walling; Hasnain Lakdawala; Yorgos Palaskas; Ashoke Ravi; Ofir Degani; Krishnamurthy Soumyanath; David J. Allstot (ISSCC, 2008)

A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS. - Stefano Pellerano; Yorgos Palaskas; Krishnamurthy Soumyanath (IEEE J. Solid State Circuits, 2008)

A mm-wave power harvesting RFID tag in 90nm CMOS. - Stefano Pellerano; Javier Alvarado Jr.; Yorgos Palaskas (CICC, 2009)

A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving. - Paolo Madoglio; Ashoke Ravi; Luis Cuellar 001; Stefano Pellerano; Parmoon Seddighrad; Ismael Lomeli; Yorgos Palaskas (ESSCIRC, 2009)

A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS. - Stefano Pellerano; Paolo Madoglio; Yorgos Palaskas (ISSCC, 2009)

A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS. - Stefano Pellerano; Paolo Madoglio; Yorgos Palaskas (IEEE J. Solid State Circuits, 2009)

A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS. - Jeffrey S. Walling; Hasnain Lakdawala; Yorgos Palaskas; Ashoke Ravi; Ofir Degani; Krishnamurthy Soumyanath; David J. Allstot (IEEE J. Solid State Circuits, 2009)

A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application. - Hongtao Xu; Yorgos Palaskas; Ashoke Ravi; Krishnamurthy Soumyanath (ESSCIRC, 2010)

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving. - Paolo Madoglio; Ashoke Ravi; Luis Cuellar 001; Stefano Pellerano; Parmoon Seddighrad; Ismael Lomeli; Yorgos Palaskas (IEEE J. Solid State Circuits, 2010)

A mm-Wave Power-Harvesting RFID Tag in 90 nm CMOS. - Stefano Pellerano; Javier Alvarado Jr.; Yorgos Palaskas (IEEE J. Solid State Circuits, 2010)

A 12-element 60GHz CMOS phased array transmitter on LTCC package with integrated antennas. - Ajay Balankutty; Stefano Pellerano; Telesphor Kamgaing; Kranti Tantwai; Yorgos Palaskas (A-SSCC, 2011)

A 31.5dBm outphasing class-D power amplifier in 45nm CMOS with back-off efficiency enhancement by dynamic power control. - Wei Tai; Hongtao Xu; Ashoke Ravi; Hasnain Lakdawala; Ofir B. Degani; L. Richard Carley; Yorgos Palaskas (ESSCIRC, 2011)

Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. - Jafar Savoj; Yiannos Manoli; Hooman Darabi; Yorgos Palaskas; Michael Moyal (IEEE J. Solid State Circuits, 2011)

A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application. - Hongtao Xu; Yorgos Palaskas; Ashoke Ravi; Masoud Sajadieh; Mohammed A. El-Tanani; Krishnamurthy Soumyanath (IEEE J. Solid State Circuits, 2011)

Session 15 overview: Mm-Wave and THz techniques: RF subcommittee. - Ehsan Afshari; Yorgos Palaskas (ISSCC, 2012)

A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management. - Kailash Chandrashekar; Stefano Pellerano; Paolo Madoglio; Ashoke Ravi; Yorgos Palaskas (ISSCC, 2012)

A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS. - Paolo Madoglio; Ashoke Ravi; Hongtao Xu; Kailash Chandrashekar; Marian Verhelst; Stefano Pellerano; Luis Cuellar 001; Mariano Aguirre; Masoud Sajadieh; Ofir B. Degani; Hasnain Lakdawala; Yorgos Palaskas (ISSCC, 2012)

A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS. - Yulin Tan; Jon Duster; Chang-Tsung Fu; Erkan Alpman; Ajay Balankutty; Chun C. Lee; Ashoke Ravi; Stefano Pellerano; Kailash Chandrashekar; Hyung Seok Kim; Brent R. Carlton; Satoshi Suzuki; et al. (VLSIC, 2012)

A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS. - Ashoke Ravi; Paolo Madoglio; Hongtao Xu; Kailash Chandrashekar; Marian Verhelst; Stefano Pellerano; Luis Cuellar 001; Mariano Aguirre-Hernandez; Masoud Sajadieh; J. E. Zarate-Roldan; Ofir Bochobza-Degani; Hasnain Lakdawala; et al. (IEEE J. Solid State Circuits, 2012)

A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement. - Wei Tai; Hongtao Xu; Ashoke Ravi; Hasnain Lakdawala; Ofir B. Degani; L. Richard Carley; Yorgos Palaskas (IEEE J. Solid State Circuits, 2012)

F1: Advanced RF transceiver design techniques. - Albert C. Jerng; Yorgos Palaskas; Eric A. M. Klumperink; Didier Belot; Songcheol Hong; Brian A. Floyd (ISSCC, 2013)

Wi-Fi RF energy harvesting for battery-free wearable radio platforms. - Vamsi Talla; Stefano Pellerano; Hongtao Xu; Ashoke Ravi; Yorgos Palaskas (IEEE RFID, 2015)

13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications. - Paolo Madoglio; Hongtao Xu; Kailash Chandrashekar; Luis Cuellar 001; Muhammad Faisal; Yee William Li; Hyung Seok Kim; Khoa Minh Nguyen; Yulin Tan; Brent R. Carlton; Vaibhav A. Vaidya; Yanjie Wang; et al. (ISSCC, 2017)

A Cellular Multiband DTC-Based Digital Polar Transmitter With -153 dBc/Hz Noise in 14-nm FinFET. - Yorgos Palaskas; Peter Plechinger; Ashoke Ravi; Ofir Degani; Rotem Banin; Eshel Gordon; Zdravko Boos; Paolo Madoglio; Jörn Angel; Jakob M. Tomasik; Sven Hampel; Petra Schubert; et al. (ESSCIRC, 2019)

Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS. - Parmoon Seddighrad; Yorgos Palaskas; Hongtao Xu; Paolo Madoglio; Kailash Chandrashekar; David J. Allstot (ISCAS, 2020)

A Cellular Multiband DTC-Based Digital Polar Transmitter With -153-dBc/Hz Noise in 14-nm FinFET. - Paolo Madoglio; Yorgos Palaskas; Jörn Angel; Jakob M. Tomasik; Sven Hampel; Petra Schubert; Peter Preyler; Thomas Mayer 003; Thomas Bauernfeind; Peter Plechinger; Ashoke Ravi; Ofir Degani; et al. (IEEE J. Solid State Circuits, 2020)