A 17-ns 4-Mb CMOS DRAM. - Takeshi Nagai; Kenji Numata; Masaki Ogihara; Mitsuru Shimizu; Kimimasa Imai; Takahiko Hara; Munehiro Yoshida; Yoshikazu Saito; Yoshiaki Asao; Shizuo Sawada; Syuso Fujii (IEEE J. Solid State Circuits, 1991)

Fault-tolerant designs for 256 Mb DRAM. - Toshiaki Kirihata; Yohji Watanabe; Hing Wong; John K. DeBrosse; Munehiro Yoshida; Daisuke Kato; Shuso Fujii; Matthew R. Wordeman; Peter Poechmueller; Stephen A. Parke; Yoshiaki Asao (IEEE J. Solid State Circuits, 1996)

Flexible test mode approach for 256-Mb DRAM. - Toshiaki Kirihata; Hing Wong; John K. DeBrosse; Yohji Watanabe; Takahiko Hara; Munehiro Yoshida; Matthew R. Wordeman; Shuso Fujii; Yoshiaki Asao; Bo Krsnik (IEEE J. Solid State Circuits, 1997)

Memory design using a one-transistor gain cell on SOI. - Takashi Ohsawa; Katsuyuki Fujita; Tomoki Higashi; Yoshihisa Iwata; Takeshi Kajiyama; Yoshiaki Asao; Kazumasa Sunouchi (IEEE J. Solid State Circuits, 2002)

A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. - Yoshihisa Iwata; Kenji Tsuchida; Tsuneo Inaba; Yui Shimizu; R. Takizawa; Yoshihiro Ueda; Tadahiko Sugibayashi; Yoshiaki Asao; Takeshi Kajiyama; Keiji Hosotani; Sumio Ikegawa; Tadashi Kai; et al. (ISSCC, 2006)

MRAM Write Error Categorization with QCKB. - Yuui Shimizu; Hisanori Aikawa; Keiji Hosotani; Naoharu Shimomura; Tadashi Kai; Yoshihiro Ueda; Yoshiaki Asao; Yoshihisa Iwata; Kenji Tsuchida; Sumio Ikegawa (MTDT, 2006)

A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory. - Yoshiaki Asao; Masayoshi Iwayama; Kenji Tsuchida; Akihiro Nitayama; Hiroaki Yoda; Hisanori Aikawa; Sumio Ikegawa; Tatsuya Kishi (DFT, 2008)

A 64Mb MRAM with clamped-reference and adequate-reference schemes. - Kenji Tsuchida; Tsuneo Inaba; Katsuyuki Fujita; Yoshihiro Ueda; Takafumi Shimizu; Yoshiaki Asao; Takeshi Kajiyama; Masayoshi Iwayama; Kuniaki Sugiura; Sumio Ikegawa; Tatsuya Kishi; Tadashi Kai; et al. (ISSCC, 2010)

A Precise Model for Cross-Point Memory Array. - Yoshiaki Asao; Fumio Horiguchi (IEICE Trans. Electron., 2016)

A Comprehensive Model for Write Disturbance in Resistive Memory Composed of Cross-Point Array. - Yoshiaki Asao; Fumio Horiguchi (IEICE Trans. Electron., 2017)