A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads. - Fumio Miyaji; Yasushi Matsuyama; Yoshikazu Kanaishi; Katsunori Seno; Takashi Emori; Yoshiaki Hagiwara (IEEE J. Solid State Circuits, 1989)

A multibit test trigger circuit for megabit SRAMs. - Fumio Miyaji; Takashi Emori; Yasushi Matsuyama; Yoshikazu Kanaishi; Katsunori Seno; Yoshiaki Hagiwara (IEEE J. Solid State Circuits, 1990)

Panel discussions: "Cool chips for the next decade". - Hideharu Amano; Tadao Nakamura; Hiroaki Kobayashi; Hironori Kasahara; Yoshiaki Hagiwara; Jeffrey L. Burns; David Brash (COOL Chips, 2017)

Multichip CMOS Image Sensor Structure for Flash Image Acquisition. - Yoshiaki Hagiwara (3DIC, 2019)