A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology. - Junji Mori; Masato Nagamatsu; Masashi Hirano; Shigeru Tanaka; Makoto Noda; Yoshiaki Toyoshima; Kazuhiro Hashimoto; Hiroyuki Hayashida; Kenji Maeguchi (IEEE J. Solid State Circuits, 1991)

High-speed CMOS I/O buffer circuits. - Manabu Ishibe; Shoji Otaka; Junichi Takeda; Shigeru Tanaka; Yoshiaki Toyoshima; Satoru Takatsuka; Shoichi Shimizu (IEEE J. Solid State Circuits, 1992)

An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation. - Tamio Ikehashi; Takayuki Miyazaki; Hiroaki Yamazaki; Atsushi Suzuki; Etsuji Ogawa; Shinji Miyano; Tomohiro Saito; Tatsuya Ohguro; Takeshi Miyagi; Yoshiaki Sugizaki; Nobuaki Otsuka; Hideki Shibata; et al. (ISSCC, 2008)

2.2um BSI CMOS image sensor with two layer photo-detector. - Hiroki Sasaki; Ai Mochizuki; Yuki Sugiura; Ryoji Hasumi; Kentaro Eda; Yoshitaka Egawa; Hirofumi Yamashita; Kenji Honda; Tatsuya Ohguro; Hisayo S. Momose; Hiroshi Ootani; Yoshiaki Toyoshima; et al. (IMSE, 2015)