2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control. - Yoshichika Fujioka; Michitaka Kameyama (ICRA (3), 1993)

Coordinate Transformation VLSI Processor for Redundant Manipulator Control. - Yoshichika Fujioka; Michitaka Kameyama; Tatsuo Higuchi 001 (J. Robotics Mechatronics, 1994)

Design of a Parallel Processor for Visual Feedback Control Based on the Reconfiguration of Word Length. - Yoshichika Fujioka; Nobuhiro Tomabechi (J. Robotics Mechatronics, 1996)

VLSI Processor System for Robotics. - Michitaka Kameyama; Yoshichika Fujioka (J. Robotics Mechatronics, 1996)

Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture. - Yoshichika Fujioka; Michitaka Kameyama (Syst. Comput. Jpn., 1999)

Design of a WSI scale parallel processor for intelligent robot control based on a dynamic reconfiguration of multi-operand arithmetic units. - Yoshichika Fujioka; Nobuhiro Tomabechi (Syst. Comput. Jpn., 2000)

VLSI architecture based on packet data transfer scheme and its application. - Yuya Homma; Michitaka Kameyama; Yoshichika Fujioka; Nobuhiro Tomabechi (ISCAS (2), 2005)

Traveling-salesman game with multiple competitors/cooperators and simultaneous move search algorithm. - Nobuhiro Tomabechi; Yoshichika Fujioka (ICE-GIC, 2009)

Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme. - Yoshichika Fujioka; Michitaka Kameyama (ISOCC, 2012)

Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme. - Shintaro Harada; Xu Bai; Michitaka Kameyama; Yoshichika Fujioka (ISMVL, 2014)