Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes. - Masahiro Nomura; Yoshifumi Ikenaga; Koichi Takeda 001; Yoetsu Nakazawa; Yoshiharu Aimoto; Yasuhiko Hagihara (IEEE J. Solid State Circuits, 2006)

A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations. - Yoshifumi Ikenaga; Masahiro Nomura; Yoetsu Nakazawa; Yasuhiko Hagihara (IEEE J. Solid State Circuits, 2008)

A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. - Yoshifumi Ikenaga; Masahiro Nomura; Shuji Suenaga; Hideo Sonohara; Yoshitaka Horikoshi; Toshiyuki Saito; Yukio Ohdaira; Yoichiro Nishio; Tomohiro Iwashita; Miyuki Satou; Koji Nishida; Koichi Nose; et al. (IEEE J. Solid State Circuits, 2012)