AC-and DC-powered subnanosecond 1-kbit Josephson cache memory design. - Yoshifusa Wada; Mutsuo Hidaka; Shuichi Nagasawa; Ichiro Ishida (IEEE J. Solid State Circuits, 1988)

Josephson memory technology. - Yoshifusa Wada (Proc. IEEE, 1989)

570-ps 13-mW Josephson 1-kbit NDRO RAM. - Shuichi Nagasawa; Yoshifusa Wada; Mutsuo Hidaka; Hisanao Tsuge; Iichiro Ishida; Shuichi Tahara (IEEE J. Solid State Circuits, 1989)