A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. - Akira Tanabe; Toshio Takeshima; Hiroki Koike; Yoshiharu Aimoto; Masahide Takada; Toshiyuki Ishijima; Naoki Kasai; Hiromitsu Hada; Kentaro Shibahara; Takemitsu Kunio; Takaho Tanigawa; Takanori Saeki; et al. (IEEE J. Solid State Circuits, 1992)

A 30-ns 256-Mb DRAM with a multidivided array structure. - Tadahiko Sugibayashi; Toshio Takeshima; Isao Naritake; Tatsuya Matano; Hiroshi Takada; Yoshiharu Aimoto; Koichiro Furuta; Mamoru Fujita; Takanori Saeki; Hiroshi Sugawara; Tatsunori Murotani; Naoki Kasai; et al. (IEEE J. Solid State Circuits, 1993)

A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM. - Nobuyuki Yamashita; Tohru Kimura; Yoshihiro Fujita; Yoshiharu Aimoto; Takashi Manabe; Shin'ichiro Okazaki; Kazuyuki Nakamura; Masakazu Yamashina (IEEE J. Solid State Circuits, 1994)

Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. - Tohru Kimura; Kazuyuki Nakamura; Yoshiharu Aimoto; Takashi Manabe; Nobuyuki Yamashita; Yoshihiro Fujita; Shin'ichiro Okazaki; Masakazu Yamashina (IEEE J. Solid State Circuits, 1995)

An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration. - Masato Motomura; Yoshiharu Aimoto; Atsufkni Shibayama; Yoshikazu Yabe; Masakazu Yamashina (FCCM, 1998)

An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield. - Kenji Noda; Koujirou Matsui; Shinya Ito; Sadaaki Masuoka; Hiroyuki Kawamoto; Nobuyuki Ikezawa; Koichi Takeda 001; Yoshiharu Aimoto; Naoto Nakamura; Hideo Toyoshima; Takahiro Iwasaki; Tadahiko Horiuchi (CICC, 2000)

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. - Koichi Takeda 001; Yoshiharu Aimoto; Noritsugu Nakamura; Hideo Toyoshima; Takahiro Iwasaki; Kenji Noda; Koujirou Matsui; Shinya Itoh; Sadaaki Masuoka; Tadahiko Horiuchi; Atsushi Nakagawa; Kenju Shimogawa; et al. (IEEE J. Solid State Circuits, 2000)

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. - Kenji Noda; Koichi Takeda 001; Koujirou Matsui; Shinya Ito; Sadaaki Masuoka; Hideaki Kawamoto; Nobuyuki Ikezawa; Yoshiharu Aimoto; Noritsugu Nakamura; Takahiro Iwasaki; Hideo Toyoshima; Tadahiko Horiuchi (IEEE J. Solid State Circuits, 2001)

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes. - Masahiro Nomura; Yoshifumi Ikenaga; Koichi Takeda 001; Yoetsu Nakazawa; Yoshiharu Aimoto; Yasuhiko Hagihara (IEEE J. Solid State Circuits, 2006)

A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. - Koichi Takeda 001; Yasuhiko Hagihara; Yoshiharu Aimoto; Masahiro Nomura; Yoetsu Nakazawa; Toshio Ishii; Hiroyuki Kobatake (IEEE J. Solid State Circuits, 2006)

Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs. - Koichi Takeda 001; Toshio Saito; Shinobu Asayama; Yoshiharu Aimoto; Hiroyuki Kobatake; Shinya Ito; Toshifumi Takahashi; Masahiro Nomura; Kiyoshi Takeuchi; Yoshihiro Hayashi (IEEE J. Solid State Circuits, 2011)