A simple method for designing a hierarchical structure transversal filter. - Akiyoshi Kawahashi; Shogo Nakanura; Yoshihiko Horio; Yukio Kadowaki (ICASSP, 1991)

Switched-capacitor Chaotic Neuron for Chaotic Neural Networks. - Yoshihiko Horio; Ken Suyama (ISCAS, 1993)

IC Implementation of Switched-Capacitor Chaotic Neuron. - Yoshihiko Horio; Ken Suyama (ISCAS, 1994)

Switched-current chaotic neural network with chaotic simulated annealing. - Nobuo Kanou; Yoshihiko Horio (ICNN, 1995)

Dynamic Associative Memory Using Switched-Capacitor Chaotic Neurons. - Yoshihiko Horio; Ken Suyama (ISCAS, 1995)

Subadaptive piecewise linear quantization for speech signal (64 kbit/s) compression. - Hiroto Saito; Isao Umoto; Akira Sasou; Shogo Nakamura; Yoshihiko Horio; Tahiro Kubota (IEEE Trans. Speech Audio Process., 1996)

An asynchronous pulse neural network model and its analog IC implementation. - Yoshihiko Horio; Hidekazu Yasuda; Mitsuru Hanagata; Kazuyuki Aihara (ICECS, 1998)

Switched-capacitor multi-internal-state chaotic neuron circuit with unipolar and bipolar output functions. - Yoshihiko Horio; Izumi Kobayashi; Masato Kawakami; Hiroshi Hayashi; Kazuyuki Aihara (ISCAS (5), 1999)

A simulated LC oscillator using multi-input floating-gate MOSFETS. - Kinya Matsuda; Yoshihiko Horio; Kazuyuki Aihara (ISCAS (3), 2001)

Influences of anti-aliasing filter on estimation of the largest Lyapunov exponent. - Shinya Nagata; Yoshihiko Horio (ISCAS (3), 2001)

Mixed analog/digital system for quadratic assignment problems. - Yukihiro Kohayashi; Takehiko Koyama; Satoshi Matsui; Yoshihiko Horio; Kazuyuki Aihara (IJCNN, 2003)

Integrated pulse neuron circuit for asynchronous pulse neural networks. - Takuya Taniguchi; Yoshihiko Horio; Kazuyuki Aihara (IJCNN, 2003)

An integrated multi-scroll circuit with floating-gate MOSFETs. - Tetsuya Fujiwara; Yoshihiko Horio; Kazuyuki Aihara (ISCAS (3), 2003)

Neuron-synapse IC chip-set for large-scale chaotic neural networks. - Yoshihiko Horio; Kazuyuki Aihara; O. Yamamoto (IEEE Trans. Neural Networks, 2003)

Mixed analog/digital chaotic neuro-computer prototype: 400-neuron dynamical associative memory. - Yoshihiko Horio; Takahide Okuno; Koji Mori (IJCNN, 2004)

Exponential chaotic tabu search hardware for quadratic assignment problems using switched-current chaotic neuron IC. - Satoshi Matsui; Yukihiro Kobayashi; Kentaro Watanabe; Yoshihiko Horio (IJCNN, 2004)

Chaotic neuro-computer prototype for quadratic assignment problems. - Koji Mori; Takahide Okuno; Yoshihiko Horio (IJCNN, 2004)

Switched-Capacitor Large-Scale Chaotic Neuro-Computer Prototype and Chaotic Search Dynamics. - Yoshihiko Horio; Takahide Okuno; Koji Mori (KES, 2004)

One-dimensional discrete-time dynamical systems circuit using floating-gate MOS peaking current sink/source. - Tomoumi Yagasaki; Yoshihiko Horio; Kazuyuki Aihara (ECCTD, 2005)

Improved chaotic neuro-computer with output-coding for quadratic assignment problems. - Koji Mon; Yoshihiko Horio; Kazuyuki Aihara (IJCNN, 2005)

An asynchronous spiking chaotic neuron integrated circuit. - Yoshihiko Horio; Takuya Taniguchi; Kazuyuki Aihara (Neurocomputing, 2005)

A mixed analog/digital chaotic neuro-computer system for quadratic assignment problems. - Yoshihiko Horio; Tohru Ikeguchi; Kazuyuki Aihara (Neural Networks, 2005)

An IC implementation of a hysteresis two-port VCCS chaotic oscillator. - Takuya Hamada; Yoshihiko Horio; Kazuyuki Aihara (ECCTD, 2007)

Adaptive Feedback Control of Chaotic Neurodynamics in Analog Circuits. - Hiroyasu Ando; Aki Nakano; Yoshihiko Horio; Kazuyuki Aihara (ISCAS, 2009)

A Multi-hysteresis VCCS and its Application to Multi-scroll Chaotic Oscillators. - Kenya Jin'no; Yoshihiko Horio; Ryosuke Domae; Kazuyuki Aihara (ISCAS, 2009)

Foreword. - Yoshihiko Horio (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Mutual Information Analyses of Chaotic Neurodynamics Driven by Neuron Selection Methods in Synchronous Exponential Chaotic Tabu Search for Quadratic Assignment Problems. - Tetsuo Kawamura; Yoshihiko Horio; Mikio Hasegawa (ICONIP (1), 2010)

A CMOS nonlinear-map circuit array for threshold-coupled chaotic maps using pulse-modulation approach. - Takashi Morie; Daisuke Atuti; Kazuki Ifuku; Yoshihiko Horio; Kazuyuki Aihara (ECCTD, 2011)

Forced chaos generator with switched CMOS active inductance. - Yusuke Tsubaki; Yoshihiko Horio; Kazuyuki Aihara (ECCTD, 2011)

Beta encoders: Symbolic Dynamics and Electronic Implementation. - Tohru Kohda; Yoshihiko Horio; Yoichiro Takahashi; Kazuyuki Aihara (Int. J. Bifurc. Chaos, 2012)

An Improved Parameter Value Optimization Technique for the Reflectionless Transmission-Line Model of the Cochlea. - Takemori Orima; Yoshihiko Horio (J. Robotics Netw. Artif. Life, 2017)

An Izhikevich Model Neuron MOS Circuit for Low Voltage Operation. - Yuki Tamura; Satoshi Moriya; Tatsuki Kato; Masao Sakuraba; Yoshihiko Horio; Shigeo Sato (ICANN (1), 2019)

Chaotic Neural Network Reservoir. - Yoshihiko Horio (IJCNN, 2019)

Short-term Prediction of Hyperchaotic Flow Using Echo State Network. - Aren Sinozaki; Kota Shiozawa; Kazuki Kajita; Takaya Miyano; Yoshihiko Horio (IJCNN, 2019)

Implementation of a Chaotic Neural Network Reservoir on a TSV/μBump Stacked 3D Cyclic Neural Network Integrated Circuit. - Yoshihiko Horio; Takemori Orima; Koji Kiyoyama; Mitsumasa Koyanagi (3DIC, 2021)

Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing. - Koji Kiyoyama; Yoshihiko Horio; Takafumi Fukushima; Hiroyuki Hashimoto; Takemori Orima; Mitsumasa Koyanagi (3DIC, 2021)

A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model. - Shigeo Sato; Satoshi Moriya; Yuka Kanke; Hideaki Yamamoto; Yoshihiko Horio; Yasushi Yuminaka; Jordi Madrenas (ICANN (5), 2021)

A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation. - Satoshi Moriya; Hideaki Yamamoto; Shigeo Sato; Yasushi Yuminaka; Yoshihiko Horio; Jordi Madrenas (IJCNN, 2022)

Secret-Key Exchange Through Synchronization of Randomized Chaotic Oscillators Aided by Logistic Hash Function. - Koshiro Onuki; Kenichiro Cho; Yoshihiko Horio; Takaya Miyano (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An Extended Spatiotemporal Contextual Learning and Memory Network Model for Hardware Implementation. - Takemori Orima; Takeru Tsuji; Yoshihiko Horio (INNS DLIA@IJCNN, 2023)

Design of Mixed-Signal LSI with Analog Spiking Neural Network and Digital Inference Circuits for Reservoir Computing. - Satoshi Moriya; Hideaki Yamamoto; Masaya Ishikawa; Yasushi Yuminaka; Yoshihiko Horio; Jordi Madrenas; Shigeo Sato (IJCNN, 2024)

Analysis of Learning Process of Synaptic Weights in Spatio-temporal Learning Networks for Hardware Implementation. - Takemori Orima; Yoshihiko Horio; Takeru Tsuji (IJCNN, 2024)

An event-driven mixed analog/digital spiking neural network circuit model for hippocampal spatiotemporal context learning and memory. - Takeru Tsuji; Takemori Orima; Yoshihiko Horio (IJCNN, 2024)

Bifurcation phenomena observed from two-variable spiking neuron integrated circuit. - Takemori Orima; Yoshihiko Horio; Satoshi Moriya; Shigeo Sato (ISCAS, 2024)