A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current. - Katsuyuki Sato; Kanehide Kenmizaki; Shoji Kubono; Toshio Mochizuki; Hidetomo Aoyagi; Michitaro Kanamitsu; Soichi Kunito; Hiroyuki Uchida; Yoshihiko Yasu; Atsushi Ogishima; Sho Sano; Hiroshi Kawamoto (IEEE J. Solid State Circuits, 1991)

Hierarchical power distribution and power management scheme for a single chip mobile processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (DAC, 2006)

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (ISSCC, 2006)

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution. - Yusuke Kanno; Yuki Kondoh; Takahiro Irita; Kenji Hirose; Ryo Mori; Yoshihiko Yasu; Shigenobu Komatsu; Hiroyuki Mizuno (IEEE J. Solid State Circuits, 2007)

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (IEEE J. Solid State Circuits, 2007)

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. - Masayuki Ito; Toshihiro Hattori; Yutaka Yoshida; Kiyoshi Hayase; Tomoichi Hayashi; Osamu Nishii; Yoshihiko Yasu; Atsushi Hasegawa; Masashi Takada; Hiroyuki Mizuno; Kunio Uchiyama; Toshihiko Odaka; et al. (ISSCC, 2008)

A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS. - Masafumi Onouchi; Yusuke Kanno; Makoto Saen; Shigenobu Komatsu; Yoshihiko Yasu; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2010)