Yoshihiro Hayashi
Orcid: 0000-0002-2060-1351
According to our database1,
Yoshihiro Hayashi
authored at least 27 papers
between 1984 and 2025.
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Bibliography
2025
Analytical Modeling of RTN with Short Dwell Time for Strict Memory Bit Error Estimation.
Proceedings of the IEEE International Reliability Physics Symposium, 2025
2024
Scaling Law of Sim2Real Transfer Learning in Expanding Computational Materials Databases for Real-World Predictions.
CoRR, 2024
Advancing Extrapolative Predictions of Material Properties through Learning to Learn.
CoRR, 2024
2023
SMiPoly: Generation of a Synthesizable Polymer Virtual Library Using Rule-Based Polymerization Reactions.
J. Chem. Inf. Model., September, 2023
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
2022
T/R Switch Composed of Three HV-MOSFETs With 12.1-μW Consumption That Enables Per-Channel Self-Loopback AC Tests and -18.1-dB Switching Noise Suppression for 3-D Ultrasound Imaging With 3072-Ch Transceiver.
IEEE Trans. Very Large Scale Integr. Syst., 2022
2020
Acceleration of Liquid-Crystalline Phase Transition Simulations Using Selectively Scaled and Returned Molecular Dynamics.
J. Chem. Inf. Model., 2020
Int. J. Softw. Innov., 2020
2019
Single-Chip 3072-Element-Channel Transceiver/128-Subarray-Channel 2-D Array IC With Analog RX and All-Digital TX Beamformer for Echocardiography.
IEEE J. Solid State Circuits, 2019
Proceedings of the Computational Science/Intelligence and Applied Informatics, 2019
T/R-Switch Composed of 3 High-Voltage MOSFETs with 12.1 µW Consumption that can Perform Per-channel TX to RX Self-Loopback AC Tests for 3D Ultrasound Imaging with 3072-channel Transceiver.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2017
27.6 Single-chip 3072ch 2D array IC with RX analog and all-digital TX beamformer for 3D ultrasound imaging.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2015
Proceedings of the Symposium on VLSI Circuits, 2015
13.4 A 6.3mW BLE transceiver embedded RX image-rejection filter and TX harmonic-suppression filter reusing on-chip matching network.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2012
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.
IEEE J. Solid State Circuits, 2012
2011
A Novel Variable Inductor Using a Bridge Circuit and Its Application to a 5-20 GHz Tunable LC-VCO.
IEEE J. Solid State Circuits, 2011
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs.
IEEE J. Solid State Circuits, 2011
2009
Proceedings of the IEEE International Conference on Systems, 2009
2008
Proceedings of the IEEE International Conference on Systems, 2008
2007
Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation.
IEICE Trans. Electron., 2007
2006
A Novel Monitoring Method of RF Characteristics Variations for Sub-0.1μm MOSFETs with Precise Gate-resistance Model.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
Proceedings of the ASP-DAC '98, 1998
1996
A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme.
IEEE J. Solid State Circuits, 1996
1990
A multiprocessor system for multiple image recognition-application to automatic routing system.
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
1984