Design of a 128-mb SOI DRAM using the floating body cell (FBC). - Takashi Ohsawa; Katsuyuki Fujita; Kosuke Hatsuda; Tomoki Higashi; Tomoaki Shino; Yoshihiro Minami; Hiroomi Nakajima; Mutsuo Morikado; Kazumi Inoh; Takeshi Hamamoto; Shigeyoshi Watanabe; Shuso Fujii; et al. (IEEE J. Solid State Circuits, 2006)

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. - Hidehiro Shiga; Daisaburo Takashima; Shinichiro Shiratake; Katsuhiko Hoya; Tadashi Miyakawa; Ryu Ogiwara; Ryo Fukuda; Ryosuke Takizawa; Kosuke Hatsuda; Fumiyoshi Matsuoka; Yasushi Nagadomi; Daisuke Hashimoto; et al. (ISSCC, 2009)

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. - Hidehiro Shiga; Daisaburo Takashima; Shinichiro Shiratake; Katsuhiko Hoya; Tadashi Miyakawa; Ryu Ogiwara; Ryo Fukuda; Ryosuke Takizawa; Kosuke Hatsuda; Fumiyoshi Matsuoka; Yasushi Nagadomi; Daisuke Hashimoto; et al. (IEEE J. Solid State Circuits, 2010)