Dynamic Multi-Context Reconfiguration Scheme for Reconfigurable Parallel Image Processing System with Three Dimensional Structure. - Takeaki Sugimura; Yuta Konishi; Yoshihiro Nakatani; Takafumi Fukushima; Hiroyuki Kurino; Mitsumasa Koyanagi (ARCS Workshops, 2005)

Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. - Yoshihiro Nakatani; Masanori Hariyama; Michitaka Kameyama (IPDPS, 2006)

Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. - Yoshihiro Nakatani; Masanori Hariyama; Michitaka Kameyama (ISMVL, 2006)

A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals? - Shota Ishihara; Noriaki Idobata; Yoshihiro Nakatani; Masanori Hariyama (J. Multiple Valued Log. Soft Comput., 2011)