A 400 K-transistor CMOS sea-of-gates array with continuous track allocation. - Masatomi Okabe; Yoshihiro Okuno; Takahiko Arakawa; Ichiro Tomioka; Takio Ohno; Tomoyoshi Noda; Masahiro Hatanaka; Yoichi Kuramitsu (IEEE J. Solid State Circuits, 1989)

A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. - Masaru Haraguchi; Tokuya Osawa; Akira Yamazaki; Chikayoshi Morishima; Toshinori Morihara; Yoshikazu Morooka; Yoshihiro Okuno; Kazutami Arimoto (ISSCC, 2007)

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Masami Nakajima; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Tetsushi Tanizaki; Takayuki Gyohten; Yoshihiro Okuno; Hiroyuki Kondo; Yukihiko Shimazu; et al. (IEEE J. Solid State Circuits, 2007)

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Tetsushi Tanizaki; Takayuki Gyohten; Katsumi Dosaka; Masami Nakajima; Katsuya Mizumoto; Kanako Yoshida; Takenobu Iwao; Tetsu Nishijima; Yoshihiro Okuno; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. - Masaru Haraguchi; Tokuya Osawa; Akira Yamazaki; Chikayoshi Morishima; Toshinori Morihara; Yoshikazu Morooka; Yoshihiro Okuno; Kazutami Arimoto (IEICE Trans. Electron., 2009)

A scalable massively parallel processor for real-time image processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Takayuki Gyohten; Tetsu Nishijima; Hiroyuki Yamasaki; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Yoshihiro Okuno; Tetsushi Koide; Hans Jürgen Mattausch; et al. (ISSCC, 2010)

A Scalable Massively Parallel Processor for Real-Time Image Processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Tetsu Nishijima; Tetsushi Tanizaki; Hiroyuki Yamasaki; Takeaki Sugimura; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Kan Murata; Kanako Yoshida; et al. (IEEE J. Solid State Circuits, 2011)