A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme. - Yasuhiro Takai; Mamoru Fujita; Kyoichi Nagata; Satoshi Isa; Shigeyuki Nakazawa; Atsunori Hirobe; Hiroaki Ohkubo; Masato Sakao; Shinichi Horiba; Tadashi Fukase; Yoshihiro Takaishi; Makoto Matsuo; et al. (IEEE J. Solid State Circuits, 2000)

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. - Tatsuya Matano; Yasuhiro Takai; Tsugio Takahashi; Yuusuke Sakito; Isamu Fujii; Yoshihiro Takaishi; Hiroki Fujisawa; Shuichi Kubouchi; Seiji Narui; Koji Arai; Makoto Morino; Masayuki Nakamura; et al. (IEEE J. Solid State Circuits, 2003)