Parasitic capacitance modeling for multilevel interconnects. - Sadahiro Tani; Yoshihiro Uchida; Makoto Furuie; Shuji Tsukiyama; BuYeol Lee; Shuji Nishi; Yasushi Kubota; Isao Shirakawa; Shigeki Imai (APCCAS (1), 2002)

VLSI architecture of digital matched filter and prime interleaver for W-CDMA. - Yoshihiro Uchida; Masanao Ise; Takao Onoye; Isao Shirakawa; Itthichai Arungsrisangchai (ISCAS (3), 2002)

Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays. - Sadahiro Tani; Yoshihiro Uchida; Makoto Furuie; Shuji Tsukiyama; BuYeol Lee; Shuji Nishi; Yasushi Kubota; Isao Shirakawa; Shigeki Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Interconnect capacitance extraction for system LCD circuits. - Yoshihiro Uchida; Sadahiro Tani; Masanori Hashimoto; Shuji Tsukiyama; Isao Shirakawa (ACM Great Lakes Symposium on VLSI, 2005)