A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator. - Yoshihisa Fujimoto; Shuichi Kawama; Kunihiko Iizuka; Masayuki Miyamoto; Daniel Senderowicz (CICC, 2000)

CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops. - Kunihiko Iizuka; Masayuki Miyamoto; Yoshiji Ohta; Takahiro Suyama; Keita Hara; Shuichi Kawama; Hirofumi Matsui; Shin'ichiro Azuma; Shigenari Taguchi; Yoshihisa Fujimoto; Daniel Senderowicz (IEEE J. Solid State Circuits, 2001)

A highly linear CMOS buffer circuit with an adjustable output impedance. - Masato Koutani; Yoshihisa Fujimoto; Masayuki Miyamoto (CICC, 2003)

A low power sample-and-hold amplifier. - Hitoshi Tani; Yoshihisa Fujimoto; Masahiko Maruyama; Hiroyuki Akada; Hiroaki Ogawa; Masayuki Miyamoto (ESSCIRC, 2003)

A delta-sigma modulator for 1-bit digital switching amplifier [audio power amplifier]. - Pascal Lo Ré; Yoshihisa Fujimoto; Hitoshi Tani; Masayuki Miyamoto (CICC, 2004)

A low-power switched-capacitor variable gain amplifier. - Yoshihisa Fujimoto; Hitoshi Tani; Masahiko Maruyama; Hiroyuki Akada; Hiroaki Ogawa; Masayuki Miyamoto (IEEE J. Solid State Circuits, 2004)

A delta-sigma modulator for a 1-bit digital switching amplifier. - Yoshihisa Fujimoto; Pascal Lo Ré; Masayuki Miyamoto (IEEE J. Solid State Circuits, 2005)

A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique. - Yusuke Kanazawa; Yoshihisa Fujimoto; Pascal Lo Ré; Masayuki Miyamoto (CICC, 2006)

An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV Receivers. - Yoshihisa Fujimoto; Yusuke Kanazawa; Pascal Lo Ré; Masayuki Miyamoto (ISSCC, 2006)

A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications. - Xuefeng Chen; Yan Wang; Yoshihisa Fujimoto; Pascal Lo Ré; Yusuke Kanazawa; Jesper Steensgaard; Gabor C. Temes (CICC, 2007)

Herman Rings of Blaschke Products of Degree 3. - Yoshihisa Fujimoto (Int. J. Bifurc. Chaos, 2009)

A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS. - Yoshihisa Fujimoto; Yusuke Kanazawa; Pascal Lo Ré; Kunihiko Iizuka (IEEE J. Solid State Circuits, 2009)