A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs. - Tohru Furuyama; Hidemi Ishiuchi; Hiroyasu Tanaka; Yoshihisa Watanabe; Yusuke Kohyama; Tohru Kimura; Kazuyoshi Muraoka; Souichi Sugiura; Kenji Natori (IEEE J. Solid State Circuits, 1990)

A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput. - Ken Takeuchi; Yasushi Kameda; Susumu Fujimura; Hiroyuki Otake; Koji Hosono; Hitoshi Shiga; Yoshihisa Watanabe; Takuya Futatsuyama; Yoshihiko Shindo; Masatsugu Kojima; Makoto Iwai; Masanobu Shirakawa; et al. (ISSCC, 2006)

A 56-nm CMOS 99-mm2 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput. - Ken Takeuchi; Yasushi Kameda; Susumu Fujimura; Hiroyuki Otake; Koji Hosono; Hitoshi Shiga; Yoshihisa Watanabe; Takuya Futatsuyama; Yoshihiko Shindo; Masatsugu Kojima; Makoto Iwai; Masanobu Shirakawa; et al. (IEEE J. Solid State Circuits, 2007)

Blind Channel Shortening for Block Transmission of Correlated Signals. - Teruyuki Miyajima; Yoshihisa Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A 151mm2 64Gb MLC NAND flash memory in 24nm CMOS technology. - Koichi Fukuda; Yoshihisa Watanabe; Eiichi Makino; Koichi Kawakami; Jumpei Sato; Teruo Takagiwa; Naoaki Kanagawa; Hitoshi Shiga; Naoya Tokiwa; Yoshihiko Shindo; Toshiaki Edahiro; Takeshi Ogawa; et al. (ISSCC, 2011)

128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode. - Yan Li; Seungpil Lee; Ken Oowada; Hao Nguyen; Qui Nguyen; Nima Mokhlesi; Cynthia Hsu; Jason Li 001; Venky Ramachandra; Teruhiko Kamei; Masaaki Higashitani; Tuan Pham; et al. (ISSCC, 2012)

A 151-mm2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology. - Koichi Fukuda; Yoshihisa Watanabe; Eiichi Makino; Koichi Kawakami; Jumpei Sato; Teruo Takagiwa; Naoaki Kanagawa; Hitoshi Shiga; Naoya Tokiwa; Yoshihiko Shindo; Takeshi Ogawa; Toshiaki Edahiro; et al. (IEEE J. Solid State Circuits, 2012)

7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology. - Mario Sako; Yoshihisa Watanabe; Takao Nakajima; Jumpei Sato; Kazuyoshi Muraoka; Masaki Fujiu; Fumihiro Kouno; Michio Nakagawa; Masami Masuda; Koji Kato; Yuri Terada; Yuki Shimizu; et al. (ISSCC, 2015)

A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology. - Mario Sako; Yoshihisa Watanabe; Takao Nakajima; Jumpei Sato; Kazuyoshi Muraoka; Masaki Fujiu; Fumihiro Kono; Michio Nakagawa; Masami Masuda; Koji Kato; Yuri Terada; Yuki Shimizu; et al. (IEEE J. Solid State Circuits, 2016)

A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm2 bit density with 3.2Gbps interface and 205MB/s program throughput. - Mario Sako; T. Nakajima; Fumihiro Kono; Takeshi Nakano; Masaki Fujiu; Junji Musha; Dai Nakamura; Naoaki Kanagawa; Yutaka Shimizu; Kosuke Yanagidaira; Tetsuaki Utsumi; T. Kawano; et al. (VLSI Technology and Circuits, 2023)

A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os. - Kosuke Yanagidaira; Mario Sako; Yasuhiro Hirashima; Junya Matsuno; Yumi Higashi; Yutaka Shimizu; Akihiro Imamoto; Kazuaki Kawaguchi; Koji Tabata; Takeshi Nakano; Yusuke Ochi; Hiroaki Hoshino; et al. (ISSCC, 2025)