A high-speed digital neural network chip with low-power chain-reaction architecture. - Kuniharu Uchimura; Osamu Saito; Yoshihito Amemiya (IEEE J. Solid State Circuits, 1992)

An all-analog expandable neural network LSI with on-chip backpropagation learning. - Takashi Morie; Yoshihito Amemiya (IEEE J. Solid State Circuits, 1994)

nu-MOS cellular-automaton devices for intelligent image sensors. - Masayuki Ikebe; Masamichi Akazawa; Yoshihito Amemiya (KES (3), 1998)

An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks. - Tetsuya Asai; Masato Koutani; Yoshihito Amemiya (IJCNN (3), 2000)

A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology. - Yusuke Kanazawa; Takashi Yamada; Tetsuya Asai; Yoshihito Amemiya (SMC, 2002)

A CMOS Reaction-Diffusion Circuit Based on Cellular-Automaton Processing Emulating the Belousov-Zhabotinsky Reaction. - Tetsuya Asai; Yuusaku Nishimiya; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

An analog neural oscillator circuit for locomotion controller in quadruped walking robot. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (IJCNN, 2003)

Biomorphic Analog Devices based on Reaction-Diffusion Systems. - Tetsuya Asai; Yoshihito Amemiya (ISMVL, 2003)

Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses. - Yusuke Kanazawa; Tetsuya Asai; Yoshihito Amemiya (J. Robotics Mechatronics, 2003)

A subthreshold MOS neuron circuit based on the Volterra system. - Tetsuya Asai; Yusuke Kanazawa; Yoshihito Amemiya (IEEE Trans. Neural Networks, 2003)

An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (IEEE Trans. Neural Networks, 2003)

A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection. - Tetsuya Asai; Yusuke Kanazawa; Tetsuya Hirose; Yoshihito Amemiya (IJCNN, 2004)

An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (ISCAS (3), 2004)

Design of an Artificial Central Pattern Generator with Feedback Controller. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (Intell. Autom. Soft Comput., 2004)

A MOS circuit for bursting neural oscillators with excitable oregonators. - Yusuke Kanazawa; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (IEICE Electron. Express, 2004)

Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. - Hiroshi Matsubara; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (IEICE Electron. Express, 2004)

A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection. - Yusuke Kanazawa; Tetsuya Asai; Masayuki Ikebe; Yoshihito Amemiya (Int. J. Robotics Autom., 2004)

Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (J. Robotics Mechatronics, 2004)

Analog current-mode CMOS implementation of central pattern generator for robot locomotion. - Kazuki Nakada; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (IJCNN, 2005)

Noise performance of single-electron depressing synapses for neuronal synchrony detection. - Takahide Oya; Tetsuya Asai; Ryo Kagaya; Yoshihito Amemiya (IJCNN, 2005)

Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (ISCAS (3), 2005)

Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. - Takahide Oya; Tetsuya Asai; Yoshihito Amemiya; Alexandre Schmid; Yusuf Leblebici (ISCAS (3), 2005)

On the fault tolerance of a clustered single-electron neural network for differential enhancement. - Takahide Oya; Alexandre Schmid; Tetsuya Asai; Yusuf Leblebici; Yoshihito Amemiya (IEICE Electron. Express, 2005)

Ultralow-Power Current Reference Circuit with Low Temperature Dependence. - Tetsuya Hirose; Toshimasa Matsuoka; Kenji Taniguchi 001; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Electron., 2005)

Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model. - Tetsuya Asai; Yusuke Kanazawa; Tetsuya Hirose; Yoshihito Amemiya (Int. J. Unconv. Comput., 2005)

Reaction-Diffusion Systems Consisting of Single-Electron Oscillators. - Takahide Oya; Tetsuya Asai; Takashi Fukui; Yoshihito Amemiya (Int. J. Unconv. Comput., 2005)

A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. - Tetsuya Asai; Masayuki Ikebe; Tetsuya Hirose; Yoshihito Amemiya (Parallel Algorithms Appl., 2005)

Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices. - Kazuki Nakada; Tetsuya Asai; Yoshihito Amemiya (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Power-supply circuits for ultralow-power subthreshold MOS-LSIs. - Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEICE Electron. Express, 2006)

Design methodologies for compact logic circuits based on collision-based computing. - Kazuhito Yamada; Ikuko N. Motoike; Tetsuya Asai; Yoshihito Amemiya (IEICE Electron. Express, 2006)

Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions. - Yoshihito Amemiya (IEICE Trans. Electron., 2006)

A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. - Tetsuya Asai; Taishi Kamiya; Tetsuya Hirose; Yoshihito Amemiya (Int. J. Bifurc. Chaos, 2006)

Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. - Gessyca Maria Tovar; Eric Shun Fukuda; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (ICONIP (2), 2007)

Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. - Gessyca Maria Tovar; Eric Shun Fukuda; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (IJCNN, 2007)

Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (ISCAS, 2007)

An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. - Akira Utagawa; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Discrete Dynamical Systems Consisting of Single-electron Circuits. - Andrew Kilinga Kikombo; Takahide Oya; Tetsuya Asai; Yoshihito Amemiya (Int. J. Bifurc. Chaos, 2007)

A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. - Motoyoshi Takahashi; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (Int. J. Bifurc. Chaos, 2007)

A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. - Kazuki Nakada; Tetsuya Asai; Tetsuya Hirose; Hatsuo Hayashi; Yoshihito Amemiya (Neurocomputing, 2007)

A Single-Electron Reaction-Diffusion Device for Computation of a Voronoi Diagram. - Takahide Oya; Tetsuya Asai; Yoshihito Amemiya (Int. J. Unconv. Comput., 2007)

CMOS Smart Sensor for Monitoring the Quality of Perishables. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEEE J. Solid State Circuits, 2007)

A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (ESSCIRC, 2008)

Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning. - Gessyca Maria Tovar; Tetsuya Asai; Yoshihito Amemiya (ICONIP (2), 2008)

Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs. - Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEICE Electron. Express, 2008)

Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. - Akira Utagawa; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

On Digital LSI Circuits Exploiting Collision-Based Fusion Gates. - Kazuhito Yamada; Tetsuya Asai; Tetsuya Hirose; Yoshihito Amemiya (Int. J. Unconv. Comput., 2008)

A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (ASP-DAC, 2009)

A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop. - Ken Ueno; Tetsuya Asai; Yoshihito Amemiya (ESSCIRC, 2009)

Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers. - Tomoki Iida; Tetsuya Asai; Eiichi Sano; Yoshihito Amemiya (ICECS, 2009)

Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits. - Andrew Kilinga Kikombo; Tetsuya Asai; Yoshihito Amemiya (ICONIP (2), 2009)

A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. - Andrew Kilinga Kikombo; Tetsuya Asai; Takahide Oya; Alexandre Schmid; Yusuf Leblebici; Yoshihito Amemiya (IJCNN, 2009)

On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. - Yusuke Tsugita; Ken Ueno; Tetsuya Asai; Yoshihito Amemiya; Tetsuya Hirose (ISCAS, 2009)

Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs. - Ken Ueno; Tetsuya Asai; Yoshihito Amemiya (ISCAS, 2009)

Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution. - Andrew Kilinga Kikombo; Tetsuya Asai; Yoshihito Amemiya (NanoNet, 2009)

Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. - Taichi Ogawa; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity. - Akira Utagawa; Tohru Sahashi; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEEE J. Solid State Circuits, 2009)

Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits. - Gessyca Maria Tovar; Tetsuya Asai; Yoshihito Amemiya (ICONIP (1), 2010)

A behavioral model of unipolar resistive RAMs and its application to HSPICE integration. - Nobuo Akou; Tetsuya Asai; Takeshi Yanagida; Tomoji Kawai; Yoshihito Amemiya (IEICE Electron. Express, 2010)

High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair. - Shin'ichi Asai; Ken Ueno; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Electron., 2010)

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs. - Yusuke Tsugita; Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEICE Trans. Electron., 2010)

A CMOS Phase-Shift oscillator Based on the conduction of Heat. - Takaaki Hirai; Tetsuya Asai; Yoshihito Amemiya (J. Circuits Syst. Comput., 2010)

A 1-muhboxW 600- hboxppm/circhboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits. - Ken Ueno; Tetsuya Hirose; Tetsuya Asai; Yoshihito Amemiya (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 0.6-4.5 GHz inductorless CMOS low noise amplifier with gyrator-C network. - Akira Kondou; Masayuki Ikebe; Junichi Motohisa; Yoshihito Amemiya; Eiichi Sano (ICECS, 2011)

Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator. - Andrew Kilinga Kikombo; Tetsuya Asai; Yoshihito Amemiya (Int. J. Unconv. Comput., 2011)