Logic Synthesis for Programmable Gate Arrays. - Rajeev Murgai; Yoshihito Nishizaki; Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1990)

Testing DSM ASIC With Static, DeltaIDDQ, And Dynamic Test Suite: Implementation And Results. - Yoshihito Nishizaki; Osamu Nakayama; Chiaki Matsumoto; Yoshitaka Kimura; Toshimi Kobayashi; Hiroyuki Nakamura (ITC, 2003)

Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. - Hiroyuki Nakamura; Akio Shirokane; Yoshihito Nishizaki; Anis Uzzaman; Vivek Chickermane; Brion L. Keller; Tsutomu Ube; Yoshihiko Terauchi (Asian Test Symposium, 2005)