Test Generation for Multiple-Threshold Gate-Delay Fault Model. - Michinobu Nakao; Yoshikazu Kiyoshige; Kazumi Hatayama; Yasuo Sato; Takaharu Nagumo (Asian Test Symposium, 2001)

Application of High-Quality Built-In Test to Industrial Designs. - Kazumi Hatayama; Michinobu Nakao; Yoshikazu Kiyoshige; Koichiro Natsume; Yasuo Sato; Takaharu Nagumo (ITC, 2002)

A 45nm 37.3GOPS/W heterogeneous multi-core SoC. - Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Shigezumi Matsui; Osamu Nishii; Atsushi Hasegawa; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Koichi Terada; Tohru Nojiri; et al. (ISSCC, 2010)

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. - Osamu Nishii; Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Yasutaka Wada; Keiji Kimura; Hironori Kasahara; Hideo Maejima (IEICE Trans. Electron., 2011)