A 45-ns 16-Mbit DRAM with triple-well structure. - Syuso Fujii; Masaki Ogihara; Mitsuru Shimizu; Munehiro Yoshida; Kenji Numata; Takahiko Hara; Shigeyoshi Watanabe; Shizuo Sawada; Tomohisa Mizuno; Junpei Kumagai; Susumu Yoshikawa; Sejii Kaki; et al. (IEEE J. Solid State Circuits, 1989)

A 17-ns 4-Mb CMOS DRAM. - Takeshi Nagai; Kenji Numata; Masaki Ogihara; Mitsuru Shimizu; Kimimasa Imai; Takahiko Hara; Munehiro Yoshida; Yoshikazu Saito; Yoshiaki Asao; Shizuo Sawada; Syuso Fujii (IEEE J. Solid State Circuits, 1991)

Graeco-Latin squares design for line detection in the presence of correlated noise. - Gerard J. Genello; Julian F. Y. Cheung; Steven H. Billis; Yoshikazu Saito (IEEE Trans. Image Process., 2000)

Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs. - Chizu Matsumoto; Yuichi Hamamura; Michinobu Nakao; Kaname Yamasaki; Yoshikazu Saito; Shun'ichi Kaneko (IEICE Trans. Electron., 2013)