16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors. - Kenichi Osada; Yoshikazu Saitoh; Eishi Ibe; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2003)

SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect. - Kenichi Osada; Ken Yamaguchi; Yoshikazu Saitoh; Takayuki Kawahara (IEEE J. Solid State Circuits, 2004)

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. - Akira Kotabe; Kenichi Osada; Naoki Kitai; Mio Fujioka; Shiro Kamohara; Masahiro Moniwa; Sadayuki Morita; Yoshikazu Saitoh (IEEE J. Solid State Circuits, 2005)