A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques. - Goro Kitsukawa; Kiyoo Itoh 001; Ryoichi Hori; Yoshiki Kawajiri; Takao Watanabe; Takayuki Kawahara; Tetsuro Matsumoto; Yutaka Kobayashi (IEEE J. Solid State Circuits, 1989)

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance. - Takao Watanabe; Goro Kitsukawa; Yoshiki Kawajiri; Kiyoo Itoh 001; Ryoichi Hori; Yoshiaki Ouchi; Takayuki Kawahara; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1989)

Substrate current reduction techniques for BiCMOS DRAM. - Takayuki Kawahara; Goro Kitsukawa; Hisayuki Higuchi; Yoshiki Kawajiri; Takao Watanabe; Kiyoo Itoh 001; Ryoichi Hori; Yutaka Kobayashi; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1989)

A 23-ns 1-Mb BiCMOS DRAM. - Goro Kitsukawa; Kazumasa Yanagisawa; Yutaka Kobayashi; Yoshitaka Kinoshita; Tatsuyuki Ohta; Tetsu Udagawa; Hitoshi Miwa; Hiroyuki Miyazawa; Yoshiki Kawajiri; Yoshiaki Ouchi; Hiromi Tsukada; Tetsuro Matsumoto; et al. (IEEE J. Solid State Circuits, 1990)

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's. - Takayuki Kawahara; Yoshiki Kawajiri; Goro Kitsukawa; Yoshinobu Nakagome; Kazuhiko Sagara; Yoshifumi Kawamoto; Takesada Akiba; Shisei Kato; Yasushi Kawase; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1991)

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's. - Takayuki Kawahara; Yoshiki Kawajiri; Goro Kitsukawa; Kazuhiko Sagara; Yoshifumi Kawamoto; Takesada Akiba; Shisei Kato; Yasushi Kawase; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1992)

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays. - Takayuki Kawahara; Takeshi Sakata; Kiyoo Itoh 001; Yoshiki Kawajiri; Takesada Akiba; Goro Kitsukawa; Masakazu Aoki (IEEE J. Solid State Circuits, 1993)

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs). - Takayuki Kawahara; Masashi Horiguchi; Yoshiki Kawajiri; Goro Kitsukawa; Tokuo Kure; Masakazu Aoki (IEEE J. Solid State Circuits, 1993)

256-Mb DRAM circuit technologies for file applications. - Goro Kitsukawa; Masashi Horiguchi; Yoshiki Kawajiri; Takayuki Kawahara; Takesada Akiba; Yasushi Kawase; Toshikazu Tachibana; Takeshi Sakai; Masakazu Aoki; Syoji Shukuri; Kazuhiko Sagara; Ryo Nagai; et al. (IEEE J. Solid State Circuits, 1993)

A charge recycle refresh for Gb-scale DRAM's in file applications. - Takayulu Kawahara; Yoshiki Kawajiri; Masashi Horiguchi; Takesada Akiba; Goro Kitsukawa; Tokuo Kure; Masakazu Aoki (IEEE J. Solid State Circuits, 1994)

A 29-mm2, 1.8-V-only, 16-Mb DINOR flash memory with gate-protected-poly-diode (GPPD) charge pump. - Yoshikazu Miyawaki; Osamu Ishizaki; Yoshihiko Okihara; Tsutomu Inaba; Fumihiko Nitta; Masaaki Mihara; Takashi Hayasaka; Kazuo Kobayashi; Tadashi Omae; Hiroshi Kimura; Satoshi Shimizu; Hiromi Makimoto; et al. (IEEE J. Solid State Circuits, 1999)