Power reduction techniques for Dynamically Reconfigurable Processor Arrays. - Takashi Nishimura; Keiichiro Hirai; Yoshiki Saito; Takuro Nakamura; Yohei Hasegawa; Satoshi Tsutsumi; Vasutan Tunbunheng; Hideharu Amano (FPL, 2008)

Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. - Yoshiki Saito; Tomoaki Shirai; Takuro Nakamura; Takashi Nishimura; Yohei Hasegawa; Satoshi Tsutsumi; Toshihiro Kashima; Mitsutaka Nakata; Seidai Takeda; Kimiyoshi Usami; Hideharu Amano (FPT, 2008)

Cache Controller Design on Ultra Low Leakage Embedded Processors. - Lei Zhao; Hui Xu; Naomi Seki; Yoshiki Saito; Yohei Hasegawa; Kimiyoshi Usami; Hideharu Amano (ARCS, 2009)

A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. - Yoshiki Saito; Toru Sano; Masaru Kato; Vasutan Tunbunheng; Yoshihiro Yasuda; Hideharu Amano (ERSA, 2009)

Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors. - Toru Sano; Yoshiki Saito; Hideharu Amano (ERSA, 2009)

Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. - Toru Sano; Yoshiki Saito; Masaru Kato; Hideharu Amano (FPL, 2009)

Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells. - Keiichiro Hirai; Masaru Kato; Yoshiki Saito; Hideharu Amano (FPT, 2009)

MuCCRA-3: a low power dynamically reconfigurable processor array. - Yoshiki Saito; Toru Sano; Masaru Kato; Vasutan Tunbunheng; Yoshihiro Yasuda; Masayuki Kimura; Hideharu Amano (ASP-DAC, 2010)

Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. - Kazuei Hironaka; Masayuki Kimura; Yoshiki Saito; Toru Sano; Masaru Kato; Vasutan Tunbunheng; Yoshihiro Yasuda; Hideharu Amano (FPT, 2010)

Geyser-2: The second prototype CPU with fine-grained run-time power gating. - Lei Zhao; Daisuke Ikebuchi; Yoshiki Saito; M. Kamata; Naomi Seki; Yu Kojima; Hideharu Amano; Satoshi Koyama; Tatsunori Hashida; Y. Umahashi; D. Masuda; Kimiyoshi Usami; et al. (ASP-DAC, 2011)

Cool Mega-Array: A highly energy efficient reconfigurable accelerator. - Nobuaki Ozaki; Yoshihiro Yasuda; Yoshiki Saito; Daisuke Ikebuchi; Masayuki Kimura; Hideharu Amano; Hiroshi Nakamura; Kimiyoshi Usami; Mitaro Namiki; Masaaki Kondo (FPT, 2011)

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. - Nobuaki Ozaki; Yoshihiro Yasuda; Mai Izawa; Yoshiki Saito; Daisuke Ikebuchi; Hideharu Amano; Hiroshi Nakamura; Kimiyoshi Usami; Mitaro Namiki; Masaaki Kondo (IEEE Micro, 2011)

Area change detection in river mouthbars at the Mekong River delta using Synthetic Aperture Radar (SAR) data. - Akiko Tanaka; Katsuto Uehara; Toru Tamura; Yoshiki Saito (IGARSS, 2012)