A 1.71-million transistor CMOS CPU chip with a testable cache architecture. - Yuichi Saito; Yukihiko Shimazu; Tom Shimizu; Kenji Shirai; Isao Fujioka; Yoshitetsu Nishiwaki; Junichi Hinata; Yoshiki Shimotsuma; Masayoshi Sakao (IEEE J. Solid State Circuits, 1993)

A study of autonomous data coherency protocol for mobile devices. - Masahiro Kuroda; Takashi Sakakura; Takashi Watanabe 001; Tadanori Mizuno; Yoshiki Shimotsuma (ICCCN, 1999)