High Speed Hardware Computation of Co-evolution Models. - Yoshiki Yamaguchi; Tsutomu Maruyama; Tsutomu Hoshino (ECAL, 1999)

A Co-processor System with a Virtex FPGA for Evolutionary Computation. - Yoshiki Yamaguchi; Akira Miyashita; Tsutomu Maruyama; Tsutomu Hoshino (FPL, 2000)

An Approach to Real-Time Visualization of PIV Method with FPGA. - Tsutomu Maruyama; Yoshiki Yamaguchi; Atsushi Kawase (FPL, 2001)

High Speed Homology Search Using Run-Time Reconfiguration. - Yoshiki Yamaguchi; Yosuke Miyajima; Tsutomu Maruyama; Akihiko Konagaya (FPL, 2002)

High Speed Homology Search with FPGAs. - Yoshiki Yamaguchi; Tsutomu Maruyama; Akihiko Konagaya (Pacific Symposium on Biocomputing, 2002)

Three-Dimensional Dynamic Programming for Homology Search. - Yoshiki Yamaguchi; Tsutomu Maruyama; Akihiko Konagaya (FPL, 2004)

Multidimensional Dynamic Programming for Homology Search. - Shingo Masuno; Tsutomu Maruyama; Yoshiki Yamaguchi; Akihiko Konagaya (FPL, 2005)

Spatiotemporal Simulation of a Single Living Cell. - Yoshiki Yamaguchi; Tsutomu Maruyama; Ryuzo Azuma; Akihiko Konagaya (FPT, 2005)

On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition. - Kyrre Glette; Jim Tørresen; Moritoshi Yasunaga; Yoshiki Yamaguchi (AHS, 2006)

Multidimensional Dynamic Programming for Homology Search on Distributed Systems. - Shingo Masuno; Tsutomu Maruyama; Yoshiki Yamaguchi; Akihiko Konagaya (Euro-Par, 2006)

Realization of the sound space environment for the radiation-tolerant space craft. - Hiroyuki Kawai; Yoshiki Yamaguchi; Moritoshi Yasunaga (ReConFig, 2006)

An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma. - Yoshiki Yamaguchi; Kenji Kanazawa; Yoshiharu Ohke; Tsutomu Maruyama (ARC, 2007)

An FPGA Implementation of Multiple Sequence Alignment Based on Carrillo-Lipman Method. - Shingo Masuno; Tsutomu Maruyama; Yoshiki Yamaguchi; Akihiko Konagaya (FPL, 2007)

High speed tablation system using an FPGA designed for distribution tables of frequent DNA subsequences. - Yoshiki Yamaguchi; Tsutomu Maruyama; Fumikazu Konishi; Akihiko Konagaya (FPL, 2007)

Bio-Inspired Functional Asymmetry Camera System. - Yoshiki Yamaguchi; Noriyuki Aibe; Moritoshi Yasunaga; Yorihisa Yamamoto; Takaaki Awano; Ikuo Yoshihara (ICONIP (2), 2007)

A Lattice Gas Cellular Automata Simulator on the Cell Broadband Engine. - Yusuke Arai; Ryo Sawai; Yoshiki Yamaguchi; Tsutomu Maruyama; Moritoshi Yasunaga (PARCO, 2007)

A bio-inspired tracking camera system. - Yoshiki Yamaguchi; Moritoshi Yasunaga; Kazuya Hayashi; Noriyuki Aibe; Yorihisa Yamamoto; Ikuo Yoshihara (Artif. Life Robotics, 2007)

Multiple Sequence Alignment Based on Dynamic Programming Using FPGA. - Shingo Masuno; Tsutomu Maruyama; Yoshiki Yamaguchi; Akihiko Konagaya (IEICE Trans. Inf. Syst., 2007)

Mesoscopic-level Simulation of Dynamics and Interactions of Biological Molecules Using Monte Carlo Simulation. - Yoshiki Yamaguchi; Tsutomu Maruyama; Ryuzo Azuma; Moritoshi Yasunaga; Akihiko Konagaya (J. VLSI Signal Process., 2007)

How fast is an FPGA in image processing? - Takashi Saegusa; Tsutomu Maruyama; Yoshiki Yamaguchi (FPL, 2008)

An adaptive pattern recognition hardware with on-chip shift register-based partial reconfiguration. - Hiroyuki Kawai; Yoshiki Yamaguchi; Moritoshi Yasunaga; Kyrre Glette; Jim Tørresen (FPT, 2008)

The Segmental-Transmission-Line: Its Design and Prototype Evaluation. - Moritoshi Yasunaga; Yoshiki Yamaguchi; Hiroshi Nakayama; Ikuo Yoshihara; Naoki Koizumi; Jung Hwan Kim (ICES, 2008)

Real-world applications on the reconfigurable-VLSI-based double-lens tracking-camera. - Moritoshi Yasunaga; Noriyuki Aibe; Yoshiki Yamaguchi; Yorihisa Yamamoto; Takaaki Awano; Ikuo Yoshihara (Artif. Life Robotics, 2008)

A reconfigurable VLSI-based double-lens tracking camera. - Moritoshi Yasunaga; Noriyuki Aibe; Yoshiki Yamaguchi; Yorihisa Yamamoto; Takaaki Awano; Ikuo Yoshihara (Artif. Life Robotics, 2008)

Tile-Based Fault Tolerant Approach Using Partial Reconfiguration. - Atsuhiro Kanamaru; Hiroyuki Kawai; Yoshiki Yamaguchi; Morisothi Yasunaga (ARC, 2009)

Performance comparison of FPGA, GPU and CPU in image processing. - Shuichi Asano; Tsutomu Maruyama; Yoshiki Yamaguchi (FPL, 2009)

Dynamic reconfiguration system for real-time video processing. - Saya Hinaga; Yoshiki Yamaguchi; Tetsuhiko Yao; Tohru Kawabe (FPL, 2009)

A visual-inspection system using a self-organizing map. - Keiko Ikeda; Moritoshi Yasunaga; Yoshiki Yamaguchi; Yorihisa Yamamoto; Ikuo Yoshihara (Artif. Life Robotics, 2009)

FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design. - Yoshiki Yamaguchi; Kuen Hung Tsoi; Wayne Luk (ARC, 2011)

A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only). - Yoshiki Yamaguchi; Kuen Hung Tsoi; Wayne Luk (FPGA, 2011)

A study of an FPGA based flexible SIMD processor. - Shoji Tanabe; Takuya Nagashima; Yoshiki Yamaguchi (SIGARCH Comput. Archit. News, 2011)

An augmented reality system with a coarse-grained reconfigurable device. - Kei Kinoshita; Daisuke Takano; Tomoyuki Okamura; Tetsuhiko Yao; Yoshiki Yamaguchi (SIGARCH Comput. Archit. News, 2012)

The study of three-dimensional multiphase-flow simulator. - Kenta Fujinami; Yoshiki Yamaguchi; Akira Sugiura; Yuetsu Kodama (FPL, 2013)

The Flexible Sound Synthesizer on an FPGA. - Suguru Ochiai; Yoshiki Yamaguchi; Yuetsu Kodama (CANDAR, 2013)

Energy Efficiency Improvement by Dynamic Reconfiguration for Embedded Systems. - Kei Kinoshita; Yoshiki Yamaguchi; Daisuke Takano; Tomoyuki Okamura; Tetsuhiko Yao (IEICE Trans. Inf. Syst., 2015)

Performance evaluation of Stratix V DE5-Net FPGA board for high performance computing. - Iman Firmansyah; Yoshiki Yamaguchi; Taisuke Boku (IC3INA, 2016)

FPGA-based Volleyball Player Tracker. - Chengzhe Li; Lai Yoong Yee; Hiroshi Maruyama; Yoshiki Yamaguchi (SIGARCH Comput. Archit. News, 2016)

A Study of TRAX Player by Template Matching. - Masataka Nakano; Yoshiki Yamaguchi (CANDAR, 2017)

Thorough analysis of PCIe Gen3 communication. - Hiroki Nakamura; Hirotaka Takayama; Yoshiki Yamaguchi; Taisuke Boku (ReConFig, 2017)

Programmable Logic Devices (PLDs) in Practical Applications. - Tsutomu Maruyama; Yoshiki Yamaguchi; Yasunori Osana (Principles and Structures of FPGAs, 2018)

Accelerating Space Radiative Transfer on FPGA using OpenCL. - Norihisa Fujita; Ryohei Kobayashi 001; Yoshiki Yamaguchi; Yuma Oobata; Taisuke Boku; Makito Abe; Kohji Yoshikawa; Masayuki Umemura (HEART, 2018)

OpenCL-ready High Speed FPGA Network for Reconfigurable High Performance Computing. - Ryohei Kobayashi 001; Yuma Oobata; Norihisa Fujita; Yoshiki Yamaguchi; Taisuke Boku (HPC Asia, 2018)

MITRACA: Manycore Interlinked Torus Reconfigurable Accelerator Architecture. - Riadh Ben Abdelhamid; Yoshiki Yamaguchi; Taisuke Boku (ASAP, 2019)

A High-Level Synthesis Design for a Scalable Hydrodynamic Simulation on OpenCL FPGA Platform. - Changdao Du; Yoshiki Yamaguchi (HEART, 2019)

FPGA-based Implementation of Memory-Intensive Application using OpenCL. - Iman Firmansyah; Changdao Du; Norihisa Fujita; Yoshiki Yamaguchi; Taisuke Boku (HEART, 2019)

Parallel Processing on FPGA Combining Computation and Communication in OpenCL Programming. - Norihisa Fujita; Ryohei Kobayashi 001; Yoshiki Yamaguchi; Taisuke Boku (IPDPS Workshops, 2019)

GPU-FPGA Heterogeneous Computing with OpenCL-Enabled Direct Memory Access. - Ryohei Kobayashi 001; Norihisa Fujita; Yoshiki Yamaguchi; Ayumi Nakamichi; Taisuke Boku (IPDPS Workshops, 2019)

MITRACA: A Next-Gen Heterogeneous Architecture. - Riadh Ben Abdelhamid; Yoshiki Yamaguchi; Taisuke Boku (MCSoC, 2019)

OpenCL Implementation of FPGA-Based Signal Generation and Measurement. - Iman Firmansyah; Yoshiki Yamaguchi (IEEE Access, 2019)

A Block-Based Systolic Array on an HBM2 FPGA for DNA Sequence Alignment. - Riadh Ben Abdelhamid; Yoshiki Yamaguchi (ARC, 2020)

FPGA-Based Computational Fluid Dynamics Simulation Architecture via High-Level Synthesis Design Method. - Changdao Du; Iman Firmansyah; Yoshiki Yamaguchi (ARC, 2020)

Condensing an overload of parallel computing ingredients into a single architecture recipe. - Riadh Ben Abdelhamid; Yoshiki Yamaguchi; Taisuke Boku (ASAP, 2020)

Accelerating Radiative Transfer Simulation with GPU-FPGA Cooperative Computation. - Ryohei Kobayashi 001; Norihisa Fujita; Yoshiki Yamaguchi; Taisuke Boku; Kohji Yoshikawa; Makito Abe; Masayuki Umemura (ASAP, 2020)

High-Performance Computation of LGCA Fluid Dynamics on an FPGA-Based Platform. - Changdao Du; Iman Firmansyah; Yoshiki Yamaguchi (ICCCS, 2020)

Toward OpenACC-enabled GPU-FPGA Accelerated Computing. - Norihisa Fujita; Ryohei Kobayashi 001; Yoshiki Yamaguchi; Kohji Yoshikawa; Makito Abe; Masayuki Umemura (CLUSTER, 2020)

A study of FPGA-based cluster computing by high-speed serial-link communication. - Ruochong Fan; Yoshiki Yamaguchi (CANDAR (Workshops), 2020)

Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA. - Norihisa Fujita; Ryohei Kobayashi 001; Yoshiki Yamaguchi; Tomohiro Ueno; Kentaro Sano; Taisuke Boku (IPDPS Workshops, 2020)

OpenCL-enabled Parallel Raytracing for Astrophysical Application on Multiple FPGAs with Optical Links. - Norihisa Fujita; Ryohei Kobayashi 001; Yoshiki Yamaguchi; Taisuke Boku; Kohji Yoshikawa; Makito Abe; Masayuki Umemura (H2RC@SC, 2020)

Multi-Hybrid Accelerated Simulation by GPU and FPGA on Radiative Transfer Simulation in Astrophysics. - Ryohei Kobayashi 001; Norihisa Fujita; Yoshiki Yamaguchi; Taisuke Boku; Kohji Yoshikawa; Makito Abe; Masayuki Umemura (J. Inf. Process., 2020)

FPGA-based implementation of a chirp signal generator using an OpenCL design. - Iman Firmansyah; Yoshiki Yamaguchi (Microprocess. Microsystems, 2020)

HBM2 Memory System for HPC Applications on an FPGA. - Norihisa Fujita; Ryohei Kobayashi 001; Yoshiki Yamaguchi; Taisuke Boku (CLUSTER, 2021)

An FPGA-based storage control with load balancing. - Naoya Umezu; Yoshiki Yamaguchi; Taisuke Boku (CLUSTER, 2021)

An efficient RTL buffering scheme for an FPGA-accelerated simulation of diffuse radiative transfer. - Kazuki Furukawa; Ryohei Kobayashi 001; Tomoya Yokono; Norihisa Fujita; Yoshiki Yamaguchi; Taisuke Boku; Kohji Yoshikawa; Masayuki Umemura (FPT, 2021)

FPGA-Based Implementation of the Stereo Matching Algorithm Using High-Level Synthesis. - Iman Firmansyah; Yoshiki Yamaguchi (MCSoC, 2021)

A Highly-Efficient and Tightly-Connected Many-Core Overlay Architecture. - Riadh Ben Abdelhamid; Yoshiki Yamaguchi; Taisuke Boku (IEEE Access, 2021)

Implementation and Performance Evaluation of Memory System Using Addressable Cache for HPC Applications on HBM2 Equipped FPGAs. - Norihisa Fujita; Ryohei Kobayashi 001; Yoshiki Yamaguchi; Taisuke Boku (Euro-Par Workshops, 2022)

FPGA-based acceleration of stereo matching using OpenCL. - Iman Firmansyah; Yoshiki Yamaguchi; Ryo Nakagawa (IC3INA, 2022)

Packed SIMD Vectorization of the DRAGON2-CB. - Riadh Ben Abdelhamid; Yoshiki Yamaguchi (MCSoC, 2022)

Accelerating Radiative Transfer Simulation on NVIDIA GPUs with OpenACC. - Ryohei Kobayashi 001; Norihisa Fujita; Yoshiki Yamaguchi; Taisuke Boku; Kohji Yoshikawa; Makito Abe; Masayuki Umemura (PDCAT, 2022)

Real-Time FPGA Implementation of FIR Filter Using OpenCL Design. - Iman Firmansyah; Yoshiki Yamaguchi (J. Signal Process. Syst., 2022)

GPU Acceleration of Multi-Object Tracking with Motion Vector Interpolation and Affine Transformation. - Yoshiki Kunimoto; Qiong Chang; Yoshiki Yamaguchi; Tsutomu Maruyama (ASAP, 2023)

Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages. - Ryohei Niwase; Hikaru Harasawa; Yoshiki Yamaguchi; Kaijie Wei; Hideharu Amano; Takefumi Miyoshi (ICFPT, 2023)

A state vector quantum simulator working on FPGAs with extensible SATA storage. - Kaijie Wei; Ryohei Niwase; Hideharu Amano; Yoshiki Yamaguchi; Takefumi Miyoshi (ICFPT, 2023)

Quantitative study of floating-point precision on modern FPGAs. - Riadh Ben Abdelhamid; Gen Kuwazawa; Yoshiki Yamaguchi (HEART, 2023)

FPGA-based detector with SiC sensing for real-time monitoring of muon beams: A preliminary report of the SCIBER-1 system in COMET Phase-α. - Yoon Jongkwan; Yoshiki Yamaguchi; Yowichi Fujita; Yoshinori Fukao; Eitaro Hamada; Tetsuichi Kishishita; Youichi Igarashi; Masayoshi Shoji; Kazuki Ueno (HEART, 2023)

GPU-FPGA-accelerated Radiative Transfer Simulation with Inter-FPGA Communication. - Ryohei Kobayashi 001; Norihisa Fujita; Yoshiki Yamaguchi; Taisuke Boku; Kohji Yoshikawa; Makito Abe; Masayuki Umemura (HPC Asia, 2023)

A cost/power efficient storage system with directly connected FPGA and SATA disks. - Ryohei Niwase; Hikaru Harasawa; Yoshiki Yamaguchi; Kaijie Wei; Hideharu Amano (MCSoC, 2023)

A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA. - Riadh Ben Abdelhamid; Yoshiki Yamaguchi; Taisuke Boku (ACM Trans. Reconfigurable Technol. Syst., 2023)

Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance. - Yuxi Tan; Masaru Nishimura; Riadh Ben Abdelhamid; Bingjie Guo; Qixiang Gao; Yoshiki Yamaguchi (HEART, 2024)

A data compressor for FPGA-based state vector quantum simulators. - Kaijie Wei; Hideharu Amano; Ryohei Niwase; Yoshiki Yamaguchi (HEART, 2024)

Low-latency and high-bandwidth communication using HSS transceivers on a Versal FPGA. - Takeo Kurosawa; Yoshiki Yamaguchi; Ryouhei Tsugami; Toshihito Fujiwara; Tatsuya Fukui; Satoshi Narikawa (ICCE, 2024)

Stereo Vision System for Crop Height Measurement Using a Monocular Camera-Equipped Drone. - Ryo Nakagawa; Yoshiki Yamaguchi; Hajime Nobuhara; Iman Firmansyah; Kai Sheng (ICCE, 2024)

FPGA-based ultra-low latency background remover. - Yoshiyuki Oshima; Yoshiki Yamaguchi; Ryouhei Tsugami; Toshihito Fujiwara; Tatsuya Fukui; Satoshi Narikawa (ICCE, 2024)

Scalable dual-instruction multiple-data processing on an efficient systolic-array architecture. - Yuxi Tan; Riadh Ben Abdelhamid; Bingjie Guo; Qixiang Gao; Masaru Nishimura; Yoshiki Yamaguchi (IPDPS (Workshops), 2024)

FPGA-Based Improved Background Subtraction for Ultra-Low Latency. - Yoshiyuki Oshima; Yoshiki Yamaguchi; Ryouhei Tsugami; Toshihito Fujiwara; Tatsuya Fukui; Satoshi Narikawa (IEEE Access, 2024)

Enhancing IoT data acquisition efficiency via FPGA-based implementation with OpenCL framework. - Iman Firmansyah; Bambang Setiadi; Agus Subekti; Heri Nugraha; Edi Kurniawan; Yoshiki Yamaguchi (Comput. Electr. Eng., 2024)

PV-VTT: A Privacy-Centric Dataset for Mission-Specific Anomaly Detection and Natural Language Interpretation. - Ryozo Masukawa; Sanggeon Yun; Yoshiki Yamaguchi; Mohsen Imani (CoRR, 2024)

FPGA-based stereo matching for crop height measurement using monocular camera. - Iman Firmansyah; Yoshiki Yamaguchi; Tsutomu Maruyama; Yuta Matsuura; Heming Zhang 004; Shin Kawai; Hajime Nobuhara (Microprocess. Microsystems, 2024)

Low-Latency Immersive Display Systems with FPGA for Remote Applications. - Den Tabata; Taiga Kobori; Yoshiki Yamaguchi; Ryouhei Tsugami; Toshihito Fujiwara; Tatsuya Fukui; Satoshi Narikawa (CCNC, 2025)

A Method of Detecting Port Bay Numbers and Optimizing Effects Under Various Weather Scenarios. - Jiazheng Li 016; Lei Ao; Kai Sheng; Yoshiki Yamaguchi (ICCE, 2025)

Quantitative Reliability Assessment for 3D LiDAR Point Cloud Data Frames. - Yuki Umemoto; Junya Sato; Yoshiki Yamaguchi; Taku Yamazaki; Takumi Miyoshi; Ryoichi Shinkuma (ICCE, 2025)

Real-Time Recursive Point Cloud Prediction for Interpolating Anomalous Frames. - Yoshiki Yamaguchi; Yuki Umemoto; Takumi Miyoshi; Taku Yamazaki; Ryoichi Shinkuma (ICCE, 2025)

Accelerating CRS Format Conversion for Sparse Matrix Computation with an FPGA. - Tomoya Yokono; Yoshiki Yamaguchi (IPDPS (Workshops), 2025)

PV-VTT: A Privacy-Centric Dataset for Mission-Specific Anomaly Detection and Natural Language Interpretation. - Ryozo Masukwa; Sanggeon Yun; Yoshiki Yamaguchi; Mohsen Imani (WACV, 2025)

Hyperdimensional Intelligent Sensing for Efficient Real-Time Audio Processing on Extreme Edge. - Sanggeon Yun; Ryozo Masukawa; Hanning Chen; Sungheon Jeong 001; Wenjun Huang 001; Arghavan Rezvani; Minhyoung Na; Yoshiki Yamaguchi; Mohsen Imani (IEEE Access, 2025)

Qu-Trefoil: Large-Scale Quantum Circuit Simulator Working on FPGA With SATA Storages. - Kaijie Wei; Hideharu Amano; Ryohei Niwase; Yoshiki Yamaguchi; Takefumi Miyoshi (IEEE Trans. Computers, 2025)